非對稱輕摻雜汲極金氧化半導體電晶體微波電性分析

Abstract

在這論文中報告 0.18 微米非對稱輕摻雜汲極功率金氧化半導體電晶體特性的設計，這類型元件不具備n型汲極伸展區，使用台積電代工一層多晶矽六層金屬標準製程，而不會需要改變任何製程參數，在相同的閘極寬度下比傳統金氧化半導體電晶體有較佳的特性。該元件具有直流崩潰電壓 6.9 V，功率密度 0.54 W/mm，最大振盪頻率 115 GHz，較佳的相鄰通道功率抑制線性度特性，在 2.4 GHz 有優異之汲級效率 52 ％ 。進而分析模型化了 0.18 微米非對稱輕摻雜汲極金氧化半導體電晶體的射頻功率特性，使用校正後之元件模型與直流電壓電流量測，雜散參數與射頻功率資料相對應，建立非對稱輕摻雜汲極功率金氧化半導體電晶體模型以製作之兩級放大器晶片之製作，具有晶片電感電容元件匹配，在增加偏壓，所量測之功率輸出增加，該晶片在 2.4 GHz 具有良好之功率特性，具有 19.6 dB 功率增益，較高之 23.3 dBm 輸出功率， 29.6 ％ 功率附加效益，在 18 dBm 輸出時具有優異之 -36 dBc 相鄰通道功率抑制線性度之特性，晶片面積僅1-mmx1.1-mm。 另外選用總寬度為 200 微米非對稱輕摻雜汲極功率金氧化半導體電晶體功率元件，利用基板磨薄技術使得矽基板僅餘 50 微米，矽基板轉移至碳化矽成為散熱基板使用，使得非對稱輕摻雜汲極金氧化半導體電晶體於碳化矽上得到DC及RF效能提昇近 6.6 ％ ，碳化矽具備比矽材料高三倍之高導熱係數，且具有高基板阻值的特性，使得該大尺寸之 50 微米矽基板非對稱輕摻雜汲極功率金氧化半導體減少了自我加熱及基板的雜散效應，因此，50 微米矽基板轉換於碳化矽之非對稱輕摻雜汲極功率金氧化半導體之功率增益、飽和輸出功率及功率附加效益等參數得以提昇。

We report the performance of 0.18 □m RF power MOSFETs with an Asymmetric-Lightly-Doped-Drain (LDD) design. Such devices do not have an n+ drain extension using a foundry-standard 1P6M process, without making any process modifications and exhibited better characteristics than conventional MOSFETs with the same gate length. The devices showed a DC breakdown voltage of 6.9 V, a 0.54 W/mm power density, 115 GHz fmax, and a good adjacent channel power ratio (ACPR) linearity, as well as a 52 % drain efficiency at 2.4 GHz .Moreover, we have modeled the RF power performance of 0.18 □m asymmetric-LDD MOSFET. Using the well-calibrated device model with good matching to measured DC I-V, S-parameters and RF power data, we have fabricated a 2.4 GHz two-stage RF power amplifier using the asymmetric-LDD MOSFET cells and on-chip matching inductors. The measured output power increases with increasing bias voltages. Good RF power performance was measured at 2.4 GHz with 19.6 dB power gain, large 23.3 dBm output power, high 29.6% PAE, excellent ACPR linearity of -36 dBc at 18 dBm and small die size of only 1-mm×1.1-mm. In this thesis, the total width 200 □m of asymmetric-LDD MOSFET (AMOSFET) cells presents the DC characteristics and radio frequency (RF) power performance improvement as high as 6.6％ with 50 □m thick silicon substrate on SiC substrate. The self-heating effect and parasitic effect of the large size AMOSFET with 50 □m thick silicon on SiC substrate is reduced due to good heat dissipation and less lossy of thinned silicon substrate and SiC substrate. Therefore, the power gain, saturation output power and power added efficiency of AMOSFET with 50 □m Si substrates mounted on SiC substrate is improved.