改良式鑲崁製程應用於奈米半導體製程及其可靠性改善之研究

Abstract

本論文研究製造一個穩定可靠的奈米積體電路製程。當積體電路微縮到奈米的程度時，可以有效的達到增加元件密度、多功能及效能的目的。然而，也因為微縮到奈米的程度而導致這些特性會隨著導線的特性而變化。鑲崁式的結構開發已成功的被應用於現今的半導體製程中以克服上述的問題。在鑲崁式結構的應用中，窄溝隔離 (Shallow Trench Isolation, STI)的製程式最先被應用的。在此製程中一個相當關鍵的技術就是化學機械研磨(Chemical Mechanical Polish, CMP)製程。尤其是在此製程的清潔步驟。一個新的清潔步驟被開發即利用多化學藥劑噴灑清潔的原理再配合刷洗效果而找出具有50%缺陷數減少即最低的金屬含量。 此外在半導體後段製程中，銅的鑲崁式結構亦被應用。金屬導線傳輸的速度會隨尺寸之縮短而更遲緩,衍生所謂電阻-電容時間延遲(RC Delay Time);在内連線結構中,使用低阻值與低介電常數是一可行且克服此一問題的方法。為了改善銅的擴散問題，一個新的阻隔層被開發。我們利用化學機械研磨所導致的淺碟效應在覆蓋上氮化鉭(Tantalum Nitride, TaN)以避免銅的擴散與氧化腐蝕。實驗結果顯示此一新的結構可以成功的改善可靠度與氧化腐蝕的問題，但一新的結構卻會因為氮化鉭的導入增加7.9%的阻值。此外，我們也研究了不同種類的銅擴散阻絕層的織構(Texture)，在氮氣流量為0到30sccm時有最大的(111)/(200) 織構比例。 再者，銅導線的表面覆蓋亦是一個重要的關鍵製程。我們研究發現不同種類的銅導線覆蓋阻絕層，如氮化矽(Silicon Nitride, SiN)、碳氮化矽(Silicon Nitricarbide, SiCN)和碳氧化矽(Silicon Oxycarbide, SiCO)等分別對低介電質材料之性質有所影響。在使用OSG (Organo-Silicate Glass)與碳氧化矽的結構中會降低相對於FSG (Fluorosilicate Glass)與氮化矽傳統結構16%的電容值。而FSG/SiCO更會降低10%的電容值。然而研究結果顯示以氮化矽作銅導線覆蓋阻絕層所得到的電子遷移現象(Electro-migration, EM)卻是最佳的。因此為了降低電容值而導入不同種類的覆蓋阻絕層必須考慮因為碳與氧的導入因而影響與銅導線的附著力的整體結果。此外，實驗結果亦顯示出以碳氧化矽作銅導線覆蓋阻絕層所得到的因應力所導致的空孔現象是比其他的阻絕層來的佳。

This thesis work studies the methods to fabricate a robust nano IC device. As integrated circuit manufacture moving to nano scale, scaling down of the device was very effective in achieving the goals of increased device density, functional complexity and performance. However, scaling down of the devices became less profitable, and speed and complexity were dependant on the characteristics of interconnects that wired the devices. Damascene structure was developed and successfully applied into semiconductor industry for the above purposes. This structure is widely used in present semi-conductor process. Shallow trench isolation (STI) process is the first-step damascene structure for nano-device in FEOL. Another key process for damascene established is Chemical Mechanical Polishing (CMP) process. Post clean of CMP process in STI is a key problem. A new modified multi-chemicals spray cleaning process for post STI CMP has been developed. This cleaning sequence provides a 50% lower level defect and metallic contamination than the traditional post-CMP cleaning process. A total cleaning formula: “APM＋HF dip 15sec＋HPM” , is capable of removing virtually all major metallic ions down to below the detection limit of TXRF. Incorporation of low resistivity and low-dielectric-constant materials in multilevel interconnect can effectively reduce capacitance, thus decreasing the transmission delay. A new scheme is develop for a barrier layer of the Cu diffusion to improve the Back-End-of-Line (BEOL) Cu reliability. According to the behavior of dishing and erosion in Cu CMP process, a completely enclosed Cu structure is developed. By capping a thin TaN layer on Cu, the Cu surface was effectively isolated from the oxidative ambient and the corrosion. The Rs of Cu containing TaNx cap provides 7.9% increment on resistance than that without TaNx cap. Furthermore, The texture of the IMP-Cu films was found to depend on the grain size of the IMP-TaNx films. The (111)/(200) ratio of the Cu seed layers had the maximum value as the nucleation sites of the TaNx deposition increased with increasing the N2 flow rate from 0 to 30 sccm. Furthermore, Cu surface capping layer is also a key process for Cu diffusion barrier layer. This part of works investigated the physical properties, thermal stability, and integrated electrical performance for SiN, SiCN and SiCO dielectric barrier films. The total capacitance of the low-k (OSG; k = 3.0)/SiCO structure can be reduced by about 16% compared to the FSG (k = 3.5)/SiN structure. On the other hand, the total capacitance of the FSG/SiCO structure can also be reduced by about 10%. But the electromigration resistance of Cu with SiN is much better than that with SiCN or SiCO film, while the SiCO structure showing the worst results. As a result, it can be seen that the option of a low-dielectric constant barrier dielectric is essential in reducing the total capacitance of interconnects. Although SiCN and SiCO achieve a reduced dielectric constant, the biggest challenge is to achieve comparable robust integration as the C and O doping into the dielectrics causes integration problems, such as poor adhesion with Cu and a higher coefficient of thermal expansion. Experimental results show that SiCO films have the best stress-induced voiding resistance as a consequence of a lower and stable temperature–stress curve, but this is offset by poor electromigration due to poor adhesion.