標題: | Architecture design of full HD JPEG XR encoder for digital photography applications |
作者: | Pan, Chia-Ho Chien, Ching-Yen Chao, Wei-Min Huang, Sheng-Chieh Chen, Liang-Gee 電控工程研究所 Institute of Electrical and Control Engineering |
關鍵字: | JPEG XR;high definition photo;Joint Photographic Experts Group (JPEG);VLSI architecture |
公開日期: | 1-八月-2008 |
摘要: | To satisfy the high quality image compression requirement, the new, JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 x 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features. |
URI: | http://dx.doi.org/10.1109/TCE.2008.4637574 http://hdl.handle.net/11536/8498 |
ISSN: | 0098-3063 |
DOI: | 10.1109/TCE.2008.4637574 |
期刊: | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS |
Volume: | 54 |
Issue: | 3 |
起始頁: | 963 |
結束頁: | 971 |
顯示於類別: | 期刊論文 |