| Title: | e-Home核心技術之研究-子計畫五：晶片上匯流排之架構設計及效能分析技術(II) Technologies on Architecture Design and Performance Analysis of On-Chip Bus(II) |
| Authors: | 黃俊達 Huang Juinn-Dar 交通大學電子工程系 |
| Issue Date: | 2005 |
| Gov't Doc #: | NSC94-2220-E009-029 |
| URI: | http://hdl.handle.net/11536/90494 https://www.grb.gov.tw/search/planDetail?id=1147310&docId=220354 |
| Appears in Collections: | Research Plans |
