| 標題: | 低溫無接面多晶矽電晶體技術開發 Development of Low-Temperature Junctionless Poly-Si Device Technologies |
| 作者: | 黃調元 HUANG TIAO-YUAN 國立交通大學電子工程學系及電子研究所 |
| 公開日期: | 2013 |
| 官方說明文件#: | NSC102-2221-E009-133 |
| URI: | http://hdl.handle.net/11536/90668 https://www.grb.gov.tw/search/planDetail?id=3086753&docId=415126 |
| Appears in Collections: | Research Plans |
- 藉由單分子層摻雜技術形成新穎的無接面多晶矽薄膜電晶體之研究 / 黃品烝;Huang, Ping-Cheng;趙天生;Chao, Tien-Sheng
- Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application / Lin, Jer-Yi;Kuo, Po-Yi;Lin, Ko-Li;Chin, Chun-Chieh;Chao, Tien-Sheng
- Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique / Su, Chun-Jung;Tsai, Tzu-I;Lin, Horng-Chih;Huang, Tiao-Yuan;Chao, Tien-Sheng
- A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs / Cheng, Ya-Chi;Chen, Hung-Bin;Chang, Chun-Yen;Cheng, Chun-Hu;Shih, Yi-Jia
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