完整后设资料纪录
DC 栏位语言
dc.contributor.author林盈达en_US
dc.contributor.authorLin Ying-Daren_US
dc.date.accessioned2014-12-13T10:32:00Z-
dc.date.available2014-12-13T10:32:00Z-
dc.date.issued2013en_US
dc.identifier.govdocNSC102-2219-E009-015zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/91301-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=2956702&docId=412868en_US
dc.description.abstract嵌入式系统测试实验室: 基准评比指标设计--总计画
在国科会嵌入式网路通讯装置评比技术与工具之研发的计画支持下,我们与
资策会合作于2011 年5 月成立资策会交大嵌入式测试实验室(Embedded
Benchmarking Lab, EBL),并且发展出一系列测试方法及工具,将其整合成EBL Test
Suite v1.0。本计画延续这项努力,有别于过去兩年较专注在对待测物原始码插
码进行剖析(profiling)与最佳化(optimization),本年度较专注在不需原始码的
评比(benchmarking)或剖析,如此比较能被进行初期合作的厂商接受。
整体计画目标是提供各种测试方法与工具彻底贯穿各层次的评比与剖析。总
计画的目标是整合子计画成果于共通测试平台,并负责开发嵌入式装置自动化控
制技术。子计画一及子计画二主要提供效能及耗能剖析工具,以top-down 的方式
检视所有软体及系统效能及耗能。子计画四及子计画五也会从硬体面向以
bottom-up 的观点來检视档案系统讀写、记忆体存取之效能。而软、硬体的效能最
终将反映在使用者操作之使用经验品质(Quality of Experience, QoE)上,因此子计画
三也会同步开发使用者介面评测服务。我们将整合子计画对软、硬体效能、耗能
剖析资讯做为最佳化參數,这些结果将有助于嵌入式系统提供CPU 排程、快取记
忆体配置、电源管理、I/O 排程以及快取缓冲演算法等控制,进而提升嵌入式系统
效能。
对于测试方案的推广,在国际化方面 EBL 和嵌入式自由软体聯盟(Open
Embedded Software Foundation, OESF)的会员工业技术研究院(ITRI)共同合作,
针对Android 装置制定测试方法及开发测试套件。在国内推广方面,EBL 也和台湾
嵌入式产业聯盟(Taiwan Embedded Industry Alliance , TEIA)合作,建立Testing
SIG,负责收集业界的各种测试需求,让EBL 可以提供更多符合业界的测试方案來
协助嵌入式产业提升竞争力。结合NBL 的成功经验,EBL 也会以三种模式进行推广,
包含委托测试服务、公开测试活动以及年度road show。
zh_TW
dc.description.abstractEmbedded Benchmarking Lab: Baseline Benchmark Design - Grand Project
Under the support of the past NSC EBL project, with III we co-founded III-NCTU
Embedded Benchmarking Lab (EBL) in May 2011. We consolidated a series of test
methodologies and tools into EBL Test Suite v1.0. Compared to the past two years with
more efforts on profiling and optimization with source codes of devices under test
(DUTs), this project focuses more on source-code-free benchmarking and profiling,
which might facilitate the initial cooperation with vendors.
The overall objective is to provide benchmarking and profiling methodologies and
tools to cover all layers. The grand project aims to integrate results from subprojects to
form common testbeds, and automate the process of testing DUTs. Subprojects 1 and 2
develop benchmarking and profiling techniques on performance and power
consumption, in a top-down manner. Subprojects 4 and 5 examine the performance of
the underlying file system access and memory usage, in a bottom-up manner. As the end
result of hardware/software performance would be reflected on the quality of
experience (QoE) of user operations, subproject 3 develops benchmarking and profiling
techniques of user interface (UI). We shall integrate the results of benchmarking and
profiling from subprojects to help optimizing overall system performance by CPU
scheduling, flash memory allocation, power management, I/O scheduling, and cache
management.
To promote the developed test solutions, we collaborate internationally with Open
Embedded Software Foundation (OESF) and its member Industrial Technology
Research Institute (ITRI) to define Android test suites. Locally we collaborate with
Taiwan Embedded Industry Alliance (TEIA) to setup Testing SIG to collect the needs
from the industry. Based on the experiences from NBL, EBL does market
communications through private testing, public testing, and annual roadshow.
en_US
dc.description.sponsorship行政院国家科学委员会zh_TW
dc.language.isozh_TWen_US
dc.title嵌入式系统测试实验室---基准评比指标设计---总计画及子计画一:嵌入式系统测试实验室---耗时评比指标设计zh_TW
dc.titleEmbedded Benchmarking Lab---Baseline Benchmark Design---Embedded Benchmarking Lab---Execution Time Benchmark Designen_US
dc.typePlanen_US
dc.contributor.department国立交通大学资讯工程学系(所)zh_TW
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