A low temperature polycrystalline silicon thin film transistor phase locked loop circuit used for clock regeneration

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tai, Ya-Hsiang	en_US
dc.contributor.author	Tseng, Chen-Yeh	en_US
dc.date.accessioned	2014-12-08T15:12:02Z	-
dc.date.available	2014-12-08T15:12:02Z	-
dc.date.issued	2007	en_US
dc.identifier.isbn	978-957-28522-4-8	en_US
dc.identifier.uri	http://hdl.handle.net/11536/9223	-
dc.description.abstract	In this paper, a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) circuit of a phase locked loop (PLL) is proposed. Its performance is discussed and its high tolerance of device variation is demonstrated.	en_US
dc.language.iso	en_US	en_US
dc.title	A low temperature polycrystalline silicon thin film transistor phase locked loop circuit used for clock regeneration	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	IDMC'07: PROCEEDINGS OF THE INTERNATIONAL DISPLAY MANUFACTURING CONFERENCE 2007	en_US
dc.citation.spage	509	en_US
dc.citation.epage	511	en_US
dc.contributor.department	顯示科技研究所	zh_TW
dc.contributor.department	Institute of Display	en_US
dc.identifier.wosnumber	WOS:000258177700131	-
顯示於類別：	會議論文