針對系統晶片 (SoC) 架構工作排程方法之探討及其模擬評估環境之研製

Full metadata record

DC Field	Value	Language
dc.contributor.author	陳正	en_US
dc.contributor.author	CHEN CHENG	en_US
dc.date.accessioned	2014-12-13T10:34:51Z	-
dc.date.available	2014-12-13T10:34:51Z	-
dc.date.issued	2002	en_US
dc.identifier.govdoc	NSC91-2213-E009-063	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/93036	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=751833&docId=142907	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	針對系統晶片 (SoC) 架構工作排程方法之探討及其模擬評估環境之研製	zh_TW
dc.title	A Study of Task Scheduling Techniques for SoC Architecture and Implementation of Its Simulation and Evaluation Environment	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學資訊工程系	zh_TW
Appears in Collections:	Research Plans

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