Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 陳正 | en_US |
dc.contributor.author | CHEN CHENG | en_US |
dc.date.accessioned | 2014-12-13T10:35:52Z | - |
dc.date.available | 2014-12-13T10:35:52Z | - |
dc.date.issued | 2001 | en_US |
dc.identifier.govdoc | NSC90-2213-E009-158 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/93631 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=656158&docId=123880 | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 數位訊號處理器 | zh_TW |
dc.subject | 指令平行化 | zh_TW |
dc.subject | 模擬評估環境 | zh_TW |
dc.subject | Digital signal processor (DSP) | en_US |
dc.subject | Instruction parallelization | en_US |
dc.subject | Simulation and evaluation environment | en_US |
dc.title | 針對多重數位訊號處理機 (DSP) 指令平行化方法之探討及其模擬評估環境之研製 | zh_TW |
dc.title | A Study of Instruction Parallelization Techniques for Multiple DSPs and Implementation of Its Simulation and Evaluation Environment | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 國立交通大學資訊工程學系 | zh_TW |
Appears in Collections: | Research Plans |
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