Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 李崇仁 | en_US |
| dc.date.accessioned | 2014-12-13T10:36:36Z | - |
| dc.date.available | 2014-12-13T10:36:36Z | - |
| dc.date.issued | 2001 | en_US |
| dc.identifier.govdoc | NSC90-2215-E009-082 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/94043 | - |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=665757&docId=126388 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 系統晶片 | zh_TW |
| dc.subject | 測試技術 | zh_TW |
| dc.subject | 晶片設計 | zh_TW |
| dc.subject | System-on-chip (SOC) | en_US |
| dc.subject | Test technique | en_US |
| dc.subject | Chip design | en_US |
| dc.title | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---總計畫 | zh_TW |
| dc.title | Verification and Testing Technology Exploitation for IP-Based SoC Design | en_US |
| dc.type | Plan | en_US |
| dc.contributor.department | 交通大學電子工程系 | zh_TW |
| Appears in Collections: | Research Plans | |
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