| Title: | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---總計畫 Verification and Testing Technology Exploitation for IP-Based SoC Design |
| Authors: | 李崇仁 國立交通大學電子工程學系 |
| Issue Date: | 2000 |
| Gov't Doc #: | NSC89-2215-E009-118 |
| URI: | http://hdl.handle.net/11536/93838 https://www.grb.gov.tw/search/planDetail?id=583933&docId=109718 |
| Appears in Collections: | Research Plans |
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