先進奈米應力結構CMOS元件性能與可靠性變異之研究

Abstract

CMOS 元件通道長度的微小化，趨動電流的提升、閘極氧化層漏電流，可分別運用應力技術 (strained technique)、high-k 加上metal gate 來克服。唯獨短通道效應或通道掺雜引起的臨限 電壓變異性(Vth Variability)目前尚未能夠良好的解決，它源自於通道中的掺雜(dopant)，在面 積很小的情況下，其分佈的不均勻(nonuniform)會影響到Vth，此效應稱之為Random Dopant Fluctuation(RDF)。另一方面，strain 技術已成為90 奈米世代以後的主流技術，由於該元件強 調mobility 的提昇以提昇電流ID(driving current)，可以預期，ID variation 將在strain 元件上 更受到重視。另一新穎的效應：稱之為Random Trap Fluctuation(RTF)，對於元件考靠性亦將 產生影響。我們延續過去在CMOS 元件應力技術的研究成果，以及發展的相關研究方法， 來探討ID variation。計劃目的有四：其一是探討strained-Si 元件CMOS 元件RDF(Random Dopant Fluctuation)導致的Vth Variation。其二是利用傳輸理論，探討造成ID variation 的各個 因素，其三是利用電流雜訊量測法（ID-RTN），探討各種元件，stress 效應下，RTF(Random Trap Fluctuation)導致的Variation 及可靠性的關聯性。最後，將建立一個多變數(multivariate) 分析法，來了解各個參數在ID variation 所佔的分量，以建立正確的strain 元件設計準則。 本計劃為期三年。第一年是運用園區廠商先進的28nm 製程研製bulk control nMOSFET 元件、 nitride-capped layer (CESL) nMOSFET 和strained Si SiC S/D 結構nMOSFET 等先進元件，經 由各不同split 元件的實驗，分析探討產生drain current variation 的電性參數，接著進行RDF 導致的Vth Variation 的研究。其次，利用製程與元件模擬，輔助了解RDF 現象，最後討論 Variation 與彈道傳輸的兩個參數（Vinj 和Bsat）間之關聯性。 第二年目標是探討 strained-Si pMOS 元件的 variation。首先是探討strained-Si pMOS 元件中， strain 造成的Vth variation。接著進行RDF 導致的Vth Variation 的研究，利用製程與元件模 擬，輔助了解RDF 現象，其次，討論彈道傳輸的兩個參數（Vinj 和Bsat）與ID variation 間 之關聯性。最後，整合二年的結論，探討nMOSFET/pMOSFET 有效控制variation 且可有效 提昇元件 ID performance 之設計準則。 第三年目標是探討 strained-Si CMOS 元件中，hot-carrier 造成的trap 分佈，它的spatial distribution 及對元件可靠性的影響。其次，運用電流雜訊量測法（ID-RTN），探討Random Trap Fluctuation 導致的 Vth 及 ID variation、以及運用傳輸理論，探討variation 和元件可靠性間 的關聯性。 總之，本計畫的進行，將發展一系列的研究方法，配合更小尺寸28nm 元件的製作，探討各 種strain CMOS 元件，RDF 及RTF 造成的Vth 及ID variation，建立有效控制variation 且可 有效提昇元件 ID performance 及reliability 之設計準則，除了學術研究外，這對於產業應用， 有立即的參考價值。

With the further scaling of CMOS devices, the driving current enhancement and gate leakage reduction can be improved by the strained technique and high-k respectively. However, only the threshold voltage (Vth) variability can not be well controlled. It comes from the channel doping with its non-uniform distribution in a small area, which is called RDF(random dopant fluctuation). On the other hand, strained-silicon technology has become the mainstream technology for 90nm and beyond. As a result of its current enhancement with mobility enhancement technique, it can be expected that the drain current variation will also be very important. Another effect, call random trap fluctuation(RTF), is believed to have great impact on the device reliability. In lieu of our experiences on the strained device technology and the associated reliability study, we will extend our study to the strain-induced ID variations. The purpose of this project are four folds, first is to study the RDF induced Vth variations and its dependence on the process and device design parameters, the second one is by applying the transport theory to find the factors which induce the ID variations, and, the third one is using the RTN(Random Telegraph Noise) technique that we developed to study the RTF induced Vth variations for devices after the stress. Finally, the above studies will be applied toward a design guideline for strain devices by considering their ID variations based on a statistical multivariate analysis method. This project includes 3 phases. In the first year, the goal is to fabricate a series of bulk- and strained-nMOS devices using 28nm node technology of a cooperated foundry R&D, for experimental study. Then, we will analyze the major electrical parameters which cause the ID variations. Followed by a study on the RDF induced Vth variations and the dependences on the process and device parameters. Furthermore, based on the transport theory, we will quantitatively determine the parameters which affect the Vth and ID variations. In the second year, the focus is on the variation of pMOSFETs. First, we will study the strain-induced Vth variations, followed by studying the origin of RDF. Also, the correlation between the transport parameter and the ID/Vth variation will be studied. Finally, device design guideline for achieving better driving current performance will be accomplished. In the third year, first we will study the hot-carrier stress induced traps and their spatial distributions. The ID-RTN measurement method will be applied to study the traps and their impact on the Vth and ID variations. The correlation between variation and device reliability will also be studied. As a whole, this proposal has been dedicated on developing an understanding of the RDF and RTF induced Vth and ID variations for various strain-Si CMOS devices. It is intended to find a better solution for suppressing the Vth and ID variations while keeping a good driving current, good reliability design for various types of strained CMOS devices. These results will be expected to be useful for developing next generation CMOS technologies with good performance and reliability. The results will also serve as a good reference for semiconductor industries.