前瞻設計變更核心技術之開發

Abstract

隨著VLSI製程技術的日益進步，IC設計的複雜度也急速升高，許多設計缺陷(design failures)因此遲至製造(manufacturing)階段才被偵測出來。為了紓解產品上市時間的壓力以及節省光罩成本，利用事先灑入的備用元件(spare cells)，只需修訂金屬層光罩(metal-layer masks)，便能達成即時修正這些缺陷的目標，設計變更(engineering change order，ECO)已是每家設計廠商的必經流程。本計畫以二年為期發展設計變更所需的核心技術為目標。 本計畫第一年：所有設計變更皆須考量電路速度是否符合要求，因此以發展timing ECO所需核心技術為著眼點。我們提出新的量測timing criticality的標準。熟知的方法是以timing slack或者是gate delay為依據，但我們發現這並不正確，我們提出應考慮允許的delay改善空間，path是否帄滑，critical path通過的多寡，以及spare cell的分布。並且，我們提出用貝茲曲線當作參考的帄滑曲線標準。貝茲曲線是電腦繪圖領域常用的帄滑曲線，常用來建立流線造型，我們將其應用在EDA領域的path smoothing的技術上，初步成果顯示有極佳效果。現有的path smoothing的技術是讓每個gate與其前後相連的gate拉近，但我們發現這麼做可能會將critical path往外擴散增加整體的path長度，相反的我們讓critical path逐漸朝向貝茲曲線收斂，得到帄滑且較短的path，進而修正timing。 本計畫第二年：因為spare cell是有限的資源，使得ECO的technology remapping與傳統的極為不同。如何在有限spare cell之下如何找到合法的technology remapping結果是我們想探討的問題。我們提出新的機制來考慮spare cell數量的限制。前人的做法在產生mapping的時候並無spare cell數量的引導，大多仰賴feasibility checker的篩選，因此可能會需要多次的搜尋才能找到合法的解。為了避免耗時的搜尋，我們提出在area-recovery的階段控管spare cell的數量限制。因此，我們能將spare cell的數量，位置，以及functionality合併考量在technology mapping的過程中。

Due to the rapidly increasing design complexity in modern IC design, more and more timing failures are detected at late stages. Without deferring time-to-market, metal-only ECO is an economical technique to correct these late-found failures. ECO has been included into the standard design flow in every design house. In this project, we aim at developing core technologies for metal-only ECO synthesis. In the first year: Timing safety is an essential requirement for ECO task. We observe that a path with good timing is desired to be geometrically smooth. Different from negative slack and gate delay used in most of prior work, we propose a new metric of timing criticality–fixability–considering the smoothness of critical paths. To measure the smoothness of a path, we use Bézier curve as the golden path. Furthermore, in order to concurrently fix timing violations, we derive the propagation property to divide violated paths into independent segments. We shall develop an efficient algorithm to fix violations based on Bézier curve smoothing, fixability identification, and the propagation property. Preliminary results show that our approach is promising. In the second year: Typically, previous works assume that the generated mapping will always be feasible. However, it may not be true since spare cells are both limited in type and quantity. In this project, we will study functional ECO, especially the technology remapping procedure with bounded resources. We will propose an area-recovery-based approach. The preliminary results show that our approach can have a good control on the spare cell usage.