低功率低電壓數位及類比積體電路之晶片實現及設計法則(IV)

Title:	低功率低電壓數位及類比積體電路之晶片實現及設計法則(IV) Implementation and Methodology for Low Power/Low Voltage Digital and Analog Integrated Circuits (IV)
Authors:	陳明哲 CHEN MING-JER 交通大學電子工程研究所
Keywords:	類比積體電路;低功率;雙極接面電晶體;次臨限金氧半導體;雜訊量測;數位積體電路;Analog integrated circuit;Low power;Bipolar junction transistor (BJT);Subthreshold MOS;Noise measurement;Digital integrated circuit
Issue Date:	1999
Gov't Doc #:	NSC88-2215-E009-061
URI:	http://hdl.handle.net/11536/94268 https://www.grb.gov.tw/search/planDetail?id=418227&docId=74195
Appears in Collections:	Research Plans

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