半導體廠WIP Profile之管理模式

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DC Field	Value	Language
dc.contributor.author	李榮貴	en_US
dc.contributor.author	LI RONG-KWEI	en_US
dc.date.accessioned	2014-12-13T10:37:21Z	-
dc.date.available	2014-12-13T10:37:21Z	-
dc.date.issued	1999	en_US
dc.identifier.govdoc	NSC88-2213-E009-032	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/94569	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=443243&docId=80223	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	在製品	zh_TW
dc.subject	晶圓製造	zh_TW
dc.subject	機器當機	zh_TW
dc.subject	派工法則	zh_TW
dc.subject	Work in process (WIP)	en_US
dc.subject	Wafer fabrication	en_US
dc.subject	Machine breakdown	en_US
dc.subject	Dispatching rule	en_US
dc.title	半導體廠WIP Profile之管理模式	zh_TW
dc.title	Constraint Time Buffer Determination Model	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學工業工程與管理系	zh_TW
Appears in Collections:	Research Plans

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