積體電路生產線上考慮缺陷群聚現象之修正良率模式

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	唐麗英	en_US
dc.contributor.author	TONG LEE-ING	en_US
dc.date.accessioned	2014-12-13T10:38:10Z	-
dc.date.available	2014-12-13T10:38:10Z	-
dc.date.issued	1998	en_US
dc.identifier.govdoc	NSC87-2213-E009-080	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/95113	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=354939&docId=63469	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	積體電路	zh_TW
dc.subject	良率模式	zh_TW
dc.subject	缺陷群聚	zh_TW
dc.subject	統計分析	zh_TW
dc.subject	類神經網路	zh_TW
dc.subject	Integrated circuit	en_US
dc.subject	Yield model	en_US
dc.subject	Defect cluster	en_US
dc.subject	Statistical analysis	en_US
dc.subject	Neural network	en_US
dc.title	積體電路生產線上考慮缺陷群聚現象之修正良率模式	zh_TW
dc.title	Modified Integrated Circuit Yield Model Using Neural Network	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學工業工程與管理系	zh_TW
顯示於類別：	研究計畫