完整後設資料紀錄
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dc.contributor.authorLiang, STen_US
dc.contributor.authorYuang, MCen_US
dc.date.accessioned2014-12-08T15:02:16Z-
dc.date.available2014-12-08T15:02:16Z-
dc.date.issued1996-11-01en_US
dc.identifier.issn0267-6192en_US
dc.identifier.urihttp://hdl.handle.net/11536/957-
dc.description.abstractAsynchronous Transfer Mode (ATM) networks are expected to support to diverse mix of traffic sources demanding different Quality Of Service (QOS) guarantees. Regarding the Earliest-Due-Date (EDD) as one of the most promising scheduling disciplines offering delay guarantees in ATM switches, we provided in our previous work a decent queueing analysis for determining the urgency number (D-i) for each service class in an effort to offer 99% delay guarantees for higher delay priority calls under various traffic loads. To further evaluate the end-to-end delay distribution for an observed call, in this paper we present the departure process analysis for the EDD discipline with two urgency numbers D-0 = 0 and D-1 = D associated with two delay-based service classes (class 0 and class 1), respectively. The EDD-based ATM switch is modelled by a discrete-time, single-server queueing system with renewal and non-renewal arrivals. Based on the queueing model, we derive the interdeparture time distribution for the observed traffic stream being multiplexed with other traffic streams. The accuracy of the analysis is confirmed by simulation results. Numerical results demonstrate the characteristic reform of the periodic traffic stream after multiplexing through an EDD-based ATM switch. Since the derived departure process becomes the arrival process of the subsequent ATM switch along the pre-established virtual route, the analysis offers the realization of end-to-end delay computation for ATM networks.en_US
dc.language.isoen_USen_US
dc.subjectAsynchronous Transfer Node (ATM)en_US
dc.subjectQuality of Service (QOS)en_US
dc.subjectEarliest-Due-Date (EDD)en_US
dc.subjectend-to-end delayen_US
dc.subjectdeparture processen_US
dc.titleDeparture process analysis for earliest-due-date scheduling discipline in ATM switchesen_US
dc.typeArticleen_US
dc.identifier.journalCOMPUTER SYSTEMS SCIENCE AND ENGINEERINGen_US
dc.citation.volume11en_US
dc.citation.issue6en_US
dc.citation.spage343en_US
dc.citation.epage352en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1996WD46300004-
dc.citation.woscount0-
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