次10奈米平面及非平面場效電晶體之通道非平衡效應: 實驗及模擬

Abstract

未來五年全球半導體工業（包括台積電）製程技術特性長度將迅速轉至十奈米以下，且 元件結構通道材料等將面臨歷史上重大轉折。在這關鍵時刻，我們向國科會提出一個 三年計晝，主要銜接先前研究成果，從一關鍵點切入：通道非平衡現象行為，由此延 伸其對十奈米以下元件特性之影響。三年内將進行下列項目：（1)萃取更多的通道非平 衡現象實驗證據，並發展出用於通道非平衡現象之背向散射模式。（2)將通道非平衡物 理模式加入自行建立的量子力學模擬器，能正確處理通道非平衡現象等並能與自行量 測及文獻數據比較吻合。（3)將通道非平衡物理模式與計算機補助設計技術整合，以預 測電流電壓特性並與自行量測及文獻數據比較吻合。（4)目標元件包含十奈米以下鰭 狀及平面場效電晶體，後者可為傳統及非傳統結構者。以及（5)最後實際展示次十奈米 之鰭狀場效電晶體最佳結構，次十奈米之傳統平面場效電晶體最佳結構，和次十奈米 之非傳統平面場效電晶體最佳結構。

In the upcoming five years, the global semiconductor industry (including TSMC) will rapidly move into a feature length of less than 10 nm in the process technology. Particularly, the device structure and the channel materials both will encounter great historical changes. At this critical moment, we propose a three-year project to continue the earlier studies around a specific point: non-equilibrium phenomena in nanometer channel, from which we want to estimate its impact on device performance with channel lengths down to 10 nm and below. The 3-year proposal includes the following items. First, we will experimentally assess more evidence of channel non-equilibrium phenomena and develop backscattering based physical model that can deal with such non-equilibrium situations. Second, we will incorporate channel non-equilibrium physical model into in-house quantum simulators, creating good agreements with our measurement data and literature values in the presence of the non-equilibrium channel. Third, we will also incorporate channel non-equilibrium physical model into TCAD simulators and expect good agreements with experimental data and literature values in the presence of the non-equilibrium channel. Fourth, the target devices will include both the FinFETs and the extended planar bulk MOSFETs with and without the conventional structure. Finally, we will practically show the optimum structures of FinFETs and the extended planar bulk MOSFETs each with the feature length down to 10 nm and beyond.