奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計

Abstract

隨著製程微縮至次-100 奈米領域，漏電、元件參數變異、及長時間可靠度 劣化己成為互補式金氧半場效電晶體靜態隨機存取記憶體的穩定度、可微縮性、 及效能的主要限制。先進微處理機所使用的快速記憶體及系統晶片(SoC) 的嵌入 式記憶體需要大容積的靜態隨機存取記憶體及超過 +/- 5 個標準差 (5σ) 的設 計規格。因此以儲存位元及/或靜態隨機存取記憶體產品層次的位元列陣為基礎 來設計的特定量測與特性化電路結構設計日益重要。與此同時, 金氧半場效電晶 體靜態隨機存取記憶體的生命週期可靠度由於受到各種長時間可靠度劣化現象, 如熱載子效應 (Hot Carrier Effect) 、 P-型場效電晶體的負偏壓溫度效應、 高電 介質金屬閘極 N-型場效電晶體的正偏壓溫度效應、時間相依介電質崩潰、輻射 性損壞等，的影響而急遽惡化。其中負偏壓溫度效應與正偏壓溫度效應使得臨界 電壓，VT，隨著使用的生命週期而偏移。因此之故，用以量測負偏壓溫度效應及 正偏壓溫度效應, 並能讓設計者施以適當的劣化加速壓温以量測及特性化其對 記憶體穩定度劣化影響的量測電路結構己成為一個重要的研發課題。 在這個 2 年的研究計劃中，我們將與智原科技，針對奈米級靜態隨機存取 記憶體的靜態雜訊邊界及負偏壓溫度效應與正偏壓溫度效應，共同研發量測與特 性化的電路結構。我們將併行研發以儲存位元為基礎 (如環型振盪器)及以靜態 隨機存取記憶體產品層次的位元列陣 (SRAM cell array) 為基礎的特定量測與特 性化電路結構及量測技術。更進一步地，我們會將研發的電路結構及量測技術應 用到靜態隨機存取記憶體的穩定度及複晶閘極 (poly-gate) 互補式金氧半場效電 晶體靜態隨機存取記憶體的負偏壓溫度效應的量測及特性化。我們更將建構一套 陣列層級讀取及寫入監/量測技術用以量測靜態隨機存取記憶體位元陣列的雜訊 邊界特性,藉此架構使得電路設計者可以得到關於靜態隨機存取記憶體穩定度更 多有意義的相關設計資訊。最後，我們將會建構一套可以整合觀察負溫度偏壓效 應/正溫度偏壓效應造成的退化效應與靜態隨機存取記憶體穩定度的架構。

With technology scaling down to deep sub-100 nm regime, leakage, variation and long-term degradation have surfaced to constrain the stability, scalability and attainable performance of CMOS SRAM. State-of-the-art processor cache memory and SoC embedded memory require large capacity SRAM with over +/-5σ design, and the ability to measure/characterize the Static Noise Margin (SNM) based on specific cell test structures and/or product level SRAM array has become ever-increasingly important. Meanwhile, the lifetime reliability of nanoscale CMOS SRAM suffers from long term degradation such as Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI, for pMOS), Poasitive Bias Temperature Instability (PBTI, for high- κ metal-gate nMOS), Time-Dependent Dielectric Breakdown (TDDB), radiation-induced damage, etc.. In particular, NBTI/PBTI cause the threshold voltage, VT, to drift over the life span of usage, thus severely degrading the stability, margin, performance, and lifetime reliability. As such, SRAM NBTI/PBTI measurement structures, which allow designers to apply relevant stresses and characterize resulting stability degradation, have become a key research subject. In this 2 year project, jointly with Faraday Technology Corporation (智原科技), we will develop measurement and characterization structures for Static Noise Margin and NBTI/PBTI for nanoscale CMOS SRAM. Both individual cell based structures (e.g. ring oscillator) and product array level techniques will be investigated. We will then apply the structures and measuring techniques to the characterization of SRAM stability and NBTI degradation (for poly-gate technology). Further, we will develop array-level measurement techniques to observe the characteristics of cells in SRAM cell array, and develop the architecture for measuring the Static Noise Margin (SNM) to provide designer with more direct and significant information about the SRAM stability and design margin. Finally, we will build up a bridge between the measurement of NBTI and PBTI degradation and the resulting impact on SRAM stability.