先進之混合信號式電路設計技術開發-子計畫一：高性能光連結系統收發機積體電路(I)

Abstract

本計畫之目標為研發高性能之多通道光收發機積體電路，以應用在短距離之高速 連結系統，進而克服電通道頻寬不足問題，達到低功耗及高速傳輸之目的。在傳送端， 將透過低電流驅動之 VCSEL 雷射二極體進行信號調變，同時研發主動式負載匹配網 路，以達到低功耗之目的。光源信號將藉由多模式光纖 (multi-mode fiber) 及光波導進 行信號傳播；在接收端，將研發新型之CMOS 光感測器並整合後級信號處理電路，以 克服傳統矽光感測器靈敏度不足問題。藉此達到高整合度、低成本、與 100 Gbps 資 料整體頻寬之目標。為達此一高傳輸速率，主要需克服之設計挑戰包含:雷射二極體 （VCSEL）與CMOS 光感測器之速度極限、多模式光纖之頻寬極限與色散所造成之符 元干擾(ISI)效應、極高速、低電壓且低電流之混合信號積體電路之設計需求等。 本計劃將採用奈米標準CMOS 技術設計一極高速之光連結系統收發機積體電路。 重點研究內容將包含整合CMOS 光感測器之高感度光電轉換系統，結合高速混合信號 前餽式 (FFE) 與迴授式 (DFE) 等化器技術之低功耗、多通道資料還原電路，高頻阻 抗匹配與位準校正技術，及高速 (100 Gbps) 內建式自我測式系統與傳輸錯誤率估計技 術。同時，本計劃將著力於電路技術之發展，以期實現高速、低錯誤率、與低功率消 耗之目標。 本計畫中傳輸接收端之各子電路模組將經由仔細之設計、模擬、佈局、檢測、與 驗證。電路之製造將委由國科會晶片設計製造中心 (CIC) 以及台灣積體電路製造股份 有限公司 (TSMC) 下線。預料本計畫之研究成果對於國內傳輸介面電路技術之發展， 將可提供直接之助益。

The objective goal of this project is to develop transceiver ICs for short reach multi-channels optical interconnects. They circumvent limited bandwidth issues of electrical links while achieving low power and high speed data transmission. At the transmitter side, low current VCSEL driver incorporating active back termination network will be developed to transmit the data through multi-mode fiber or on chip waveguide. At the receiver side, novel CMOS-PDs integrated with signal conditioning circuitries will be developed to detect the light source and boost their responsivity, so as to accomplish high integration, low cost, and 100 Gbps bandwidth design goals. To achieve the target specifications, the major design issues include speed limitation of VCSEL, bandwidth limitations of multi-mode fiber, dispersion induced inter symbol interference, and the challenges of ultra high speed, low voltage and low current mixed-signal IC designs, etc. The ultra high speed optical transceivers will be designed in nano meter CMOS technologies. The major working tasks include high sensitivity O/E converters with CMOS photo detectors, high speed mixed-mode feed-forward (FFE) and decision feedback equalizer (DFE) integrated with multi-channel, low power clock and data recovery circuit, impedance matching and power control circuits, and 100 Gbps build in self test (BIST) and BER measurement circuits. Furthermore, novel circuit techniques will be explored to achieve the ultimate goal of a high speed, low bit error rate, and low power consumption transceiver system. All the sub-circuits of the high speed transceiver will be carefully designed, simulated, laid-out, verified, and measured. Fabrication will be coordinated by Chip Implementation Center (CIC) and Taiwan Semiconductor Manufacturing Company (TSMC). Circuit techniques come out with this project would be beneficial to the developing of high speed interface circuits for domestic industry.