Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 李毅郎 | en_US |
| dc.contributor.author | Li Yih-Lang | en_US |
| dc.date.accessioned | 2014-12-13T10:42:16Z | - |
| dc.date.available | 2014-12-13T10:42:16Z | - |
| dc.date.issued | 2014 | en_US |
| dc.identifier.govdoc | MOST103-2220-E009-010 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/99050 | - |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=8279078&docId=437579 | en_US |
| dc.description.sponsorship | 科技部 | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | 以資料分析為導向之新型態電子設計自動化研究---總計畫暨子計畫三：利用特徵擷取技術應用於電路與佈局層級的智慧型電路表示法( I ) | zh_TW |
| dc.title | Smart Physical- and Schematic-Level Circuit Representation through Feature Extraction( I ) | en_US |
| dc.type | Plan | en_US |
| dc.contributor.department | 國立交通大學資訊工程學系（所） | zh_TW |
| Appears in Collections: | Research Plans | |
