完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 周世傑 | en_US |
dc.contributor.author | JOU SHYH-JYE | en_US |
dc.date.accessioned | 2014-12-13T10:42:17Z | - |
dc.date.available | 2014-12-13T10:42:17Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.govdoc | NSC100-2220-E009-029 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/99055 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=2311784&docId=361369 | en_US |
dc.description.abstract | 由於高品質多媒體的應用與傳輸需求,室內億級資料無線傳輸接收機將成為次世代的主流。對於 5Gbps 以上資料無線傳輸目前尚有許多挑戰,而且關鍵技術也尚待發展:(1) 高規格的高頻元件(60 GHz 上下),若使用CMOS 製程,製造不易且成本很高。因此,如果用數位訊號處理技術補償高頻元件的 非理想性(包括相位雜訊與I/Q 不平衡等),將能在晶片成本上得到相當大的好處。(2) 在802.15.3c 及 802.11ad 兩種規格中,皆要求OFDM 和SC 兩種模式。因此,發展針對面積及功耗最佳化的雙模式架 構為一大挑戰。(3) 基頻電路必須工作在非常高的時脈 (約500MHz,實際時脈依平行化的程度而定)。 因此,演算法與硬體架構必須密切配合,在平行化的同時降低功耗。(4) 先進製程操作在高速的狀況 下,PVT 變異將使電路本身的運作有著類似隨機的錯誤行為。為使此隨機錯誤行為符合通訊行為要 求,每個模組必須考慮本身的隨機運算錯誤行為,使其符合系統的SNR 與BER 要求並進一步降低功 耗。 根據先前室內無線基頻系統的研究成果,次世代億級(超過5Gbps)基頻傳輸接收機的主要目標為: (1) 考慮高頻(60 GHz RF) / 類比前段相位雜訊、I/Q 不平衡及非線性類比數位轉換器之等化誤差,以 數位訊號處理技術補償、更正,藉此改善非理想效應並提高SNR。(2) 以802.15.3c 及802.11ad 兩系 統規格為測試平台,發展資料傳輸速率大於5Gbps 且可手持之次世代室內無線接收機系統單晶片目標 功率為1W 以下。(3) 發展可用於使用奈米級CMOS 製程的高速通訊基頻之隨機DSP 模組。 | zh_TW |
dc.description.abstract | Indoor wireless transceiver with Gbps data rate will become the next generation main stream due to high quality multimedia applications and transmission requirement. For wireless Gbps transmission, there are several challenges and key techniques that shall be developed: (1) High radio frequency devices (60 GHz range) requires very high specifications and if implemented by CMOS process, the challenges are very high and costly. It will get large benefit for cost by applying digital signal processing techniques to compensate non-ideal effect of radio frequency devices, including phase noise and I/Q imbalance. (2) In standard like 802.15.3c and 802.11ad, there are OFDM and SC mode. Developing dual mode architectures with sharing to optimize area and power consumption is a great challenge. (3) The baseband shall work at very high clock rate (like 500 MHz, depending on the number of parallelism). Thus, algorithm and architectures shall work together to make parallelism possible and at the same reduce power consumption. (4) For advanced process working at very high speed, the PVT variation makes the circuit itself work like a kind of stochastic behavior. To match the stochastic behavior with communication behavior, each module shall consider its stochastic computing behavior that meet the system SNR and BER requirement and in the same time to reduce power consumption. Based on the achievement of our previous works on indoor wireless baseband system, the major goals for the next generation above 5 Gbps wireless baseband transceiver are: (1) Take the 60GHz RF/analog front-end phase noise, I/Q unbalance and nonlinear ADC quantization error into system consideration and do digital compensation, correction or cooperation to ease the non-ideal effect and enhance SNR. (2) Take 802.15.3c and 802.11ad as test systems, develop a next generation wireless indoor baseband receiver SOC with above 5 Gbps and hand held capability. The target goal is make the baseband receiver with power below 1W (3) Develop stochastic DSP modules for high-speed communication baseband for future nano-scale CMOS process. | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | 次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP-子計畫五:次世代室內無線五十億位元傳輸率之基頻傳收機及其隨機信號處理模組( I ) | zh_TW |
dc.title | Development of Next Generation 5-Gbps Wireless Indoor Baseband Transceiver with Stochastic Ip | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 國立交通大學電子工程學系及電子研究所 | zh_TW |
顯示於類別: | 研究計畫 |