次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP-總計畫( I )

Abstract

本計畫目標在於開發次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP 前瞻之室內億級位元傳輸率基頻傳收機之SOC 設計技術及相關之關鍵性智產平台與設計法則。計畫 將以802.15.3c/802.11.ad 之57~64GHz 的免執照頻帶及802.11.ac 為測試平台並發展次世代智慧型室內 無線區域網路關鍵系統技術與系統。每個模組必須考慮本身的隨機運算(Stochastic Computing)錯誤行 為，使其符合系統的SNR 與BER 要求並進一步降低功耗。計畫目標是發展下列關鍵技術： (1) 次世代智慧型室內無線區域網路關鍵系統技術之研發。 (2) 次世代室內無線五十億位元傳輸率之基頻傳收機SOC。 (3) 針對通訊數位訊號處理器從功能單元層級到系統層級之可靠性驅策的隨機性合成技術。 (4) 適用於十億位元以上之前瞻頻域多模無線處理器架構研究。 (5) 隨機信號處理模組與具可變長度延遲資料路徑的高效能隨機ASIP 處理器設計。 (6) 前瞻無線寬頻多模、具五十億級位元以上接收功能之綠能基頻訊號編解碼器研究設計。 這些技術分在 6 個子計畫與總計畫執行，於三年中研發完成。最後也將以所設計之室內五十億級位 元傳輸率之無線基頻傳收機之各種規格作多模式之雛型與應用展示。

The goal of this project is to develop next generation intelligent wireless indoor 5-Gbps transceiver systems and applications for Wireless Personal Area Network (WPAN) baseband transceiver. We will take 802.15.3c/802.11.ad(57~64GHz)及802.11.ac (5GHz) as test platform and develop key technologies for next generation intelligent wireless indoor 5-Gbps transceiver systems。Furthermore, each baseband module will consider stochastic computing for future advanced nano-CMOS circuit behavior. By doing so, each module can fulfill the system SNR and BER requirement and in the same reduce power dissipation. The goals of this project include： (1) The Research and Development on the Key System Techniques for Next Generation Intelligent Indoor Wireless Local Area Networks. (2) Development of Next Generation 5-Gbps Wireless Indoor Baseband Transceiver SOC。 (3) Reliability-Driven Stochastic Synthesis Technology from Functional Unit Level to System Level for Communication DSP. (4) Architecture of Multi-mode Green Frequency-Domain Wireless Processor Unit (FD WPU) for Advanced Multi-Gbps Wireless Applications (5) Stochastic ASIP Processor with Variable-Latency Data-path for Next Generation Intelligent Wireless Indoor Multi-Gbps Applications。 (6) Design of Multi-mode Green Baseband Signal Coder/Decoder for Advanced Broadband Multi-Gbps Wireless Communication All these core techniques will be developed by group project and six subprojects in three years. In the final year, we will use platform with the developed IPs to do system prototyping and application demonstration.