無介面矽奈米線元件研究(I)

Abstract

本研究擬利用電子束微影(E-beam Lithography)與側壁邊襯(side-wall spacer)技術在(100) 絕緣矽(SOI)矽晶基材上研製無介面矽奈線電晶體。與傳統MOSFET 利用介面(junctions) 的形成，經由閘極對通道位能的調變，控制電流的有無不同之處，無介面矽奈線電晶體 擁有高度參雜通道(channel)，因此其元件本質時間延遲(intrinsic time delay)、載子遷移 率受通道長度奈米化與溫度擾動的影響，都預期比傳統元件小，同時製程整合的thermal budget 也因高度參雜通道容易控制。因此、本計畫第一年擬研製無介面矽奈線電晶體元 件，經熱氧化將矽奈線直徑控制在30 奈米以下，同時量測分析環繞閘極與三面閘極元 件的特性，另外、也會進行閘極控制之能帶對能帶穿隧的量測分析。第二年擬研製無介 面矽奈線非揮發記憶元件，比較奈米晶體與ONO 堆疊在環繞閘極與三面閘極介電層中 的元件特性。計畫第三年擬將矽奈米線的直徑推至10~15 奈米，同時研製多位元 (multiple-bit) 存取之無介面矽奈線非揮發記憶元件。本計畫將於變溫度(4.2K~450K) 下，經由變溫I-V/C-V 量測，觀察無介面矽奈米線電晶體的電性與無介面矽奈米線非揮 發記憶元件的存取穩定性、電流/電壓特性、不同program/erase 的穿隧現象如channel hot electrons 或Folwer-Nordheim 等將元件特性最佳化。第三年也將研製單個(或數個) 奈米 晶體或ONO堆疊做為懸浮閘的無介面矽奈米線非揮發記憶元件，並依實驗量測與TCAD 模擬建立無介面矽奈線元件相關理論模型。

Combining the e-beam lithography and side-wall spacer patterning technique, junctionless silicon nanowire devices will be fabricated and studied. In traditional nano MOSFET (either tri-gate or gate-all-around, GAA, structure), the conductance of device is controlled by the gate bias which change the channel potential. In junctionless silicon nanowire devices, due to its heavily doped active channel, no junctions exist between channel and contacts. Also due to its heavily doped channel, the intrinsic time delay、the mobility degradation due to the gate-length scaling and the mobility variation due to change of temperature are expected to be minimized compared to its counterpart, the traditional MOSFET. Moreover, the thermal budget in the device integration is also released. In the first year of this study, junctionless silicon nanowire transistors will be investigated. The diameter of silicon nanowire will be controlled under 30 nm using thermal oxidation technique. A comparison between traditional nanowire (tri-gate and GAA) devices and junctionless silicon nanowire transistors (tri-gate and GAA) will be investigated. Also, the gate-controlled band-to-band tunneling will be studied. In the second year of study, junctionless silicon nanowire nonvolatile memory devices will be fabricated and investigated. Different charge storage centers including nanocrystals and ONO stack will be embedded into the gate dielectrics for tri-gate and GAA structures. In the third year, silicon nanowire will be further reduced down to 10~15 nm via thermal oxidation. The variable-temperature IV/CV measurements will be conducted for devices characteristics including channel hot electrons injection or Folwer-Nordheim tunneling mechanisms. Junctionless silicon nanowire nonvolatile memory device with multiple-bit configuration will also be demonstrated. At the end of this three-year study, junctionless silicon nanowire nonvolatile memory device with few nanocrystals and junctionless silicon nanowire nonvolatile memory device with ONO stack (15×30 nm2) will be demonstrated. The devices models will be constructed based the experimental measurements and TCAD simulations.