次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP-子計畫六：適用於室內五十億級位元傳輸率應用之具可變長度延遲資料路徑的高效能隨機ASIP處理器設計( I )

Abstract

現今高階製程技術容易受到電壓及溫度變異，造成電路行為的不確定性。晶片良率受到影響，大幅提高製造成本。傳統透過最壞情況設計，寄望硬體完全隱藏不確定性的設計方式，很快將不敷使用。近年來許多相關研究轉而透過隨機運算技術，允許錯誤發生，但透過軟硬體技術降低錯誤的發生率及影響範圍，確保系統行為正確性。在本計劃中，我們利用電路中的資料相依延遲的特性，設計一動態值域偵測乘法器。此乘法器故意放鬆合成的時序限制條件，允許錯誤的發生。利用值域偵測電路，偵測每一次運算中被乘數及乘數的值域，藉以修正乘積中的前導符號，大幅改善乘積的準確程度。配合軟硬體協同設計平台，可針對特定應用最佳化，提升隨機運算效率。我們以一具有隨機計算特性的人臉偵測器測試程式來進行模擬及數據分析。在維持與傳統乘法器同樣的人臉偵測率前提之下，動態值域偵測乘法器可以減少11.7%的功率消耗以及6.1%的整體面積。

In advanced technologies, severe process, voltage and temperature variations and the resulting uncertainties in the circuit behavior greatly decrease chip yields and raise manufacturing costs. Traditional IC design totally conceals uncertainties through worst-case design, which will introduce vast overhead in future. Recently, quite a few researches turn to adopt stochastic computing. Computation errors are allowed while the error rate and error power are depressed using hardware and software techniques to assure correctness of system behavior. In this project, we take advantage of data-dependent latency to design dynamic range detection array multiplier. Timing constraint of the multiplier is deliberately relaxed and the computation errors are controlled by range detect unit. Range of multiplicand and multiplier are utilized to estimate range of product. Influence of computation errors can thus been alleviated. With the hardware and software co-simulation platform, the multiplier can be optimized according to specific applications. We take object detection as an example to evaluate proposed multiplier. The simulation shows the propose multiplier can save 6.1% area and 11.7% power consumption from conventional multiplier while maintaining the similar outcome in object detection.