GreenArmy：綠色微雲伺服系統晶片平台技術-子計畫二：綠色微雲伺服系統晶片之新興記憶體與儲存架構( I )

Abstract

雖然增加單一晶片中的核心數是未來的趨勢，但其成長的速度會遇到瓶頸，其原因在於晶片外溝通的頻寬成長的速度遠小於晶片內核心成長。另外，傳統的快取(cache)架構設計會產生不必要的能量消耗和限制效能表現。因此，許多關於記憶體系統以及晶片內溝通的研究想要解決以上問題。此篇論文中，我們提出階層性的快取分享概念，以達到覆載平衡(load-balance)和有效的溝通機制。藉由超低延遲環型晶片網路(Single-Cycle Ring)提供延遲及能量的減少，我們提出一個稱為Snoop2的無一致性快取記憶體系統並用在第一層快取上，以達到第一層快取分享的目的。Snoop2無一致性快取記憶體系統的目的在於提供有效的最佳化方法，讓核心使用最大的快取使用量，除此之外，提供一個有效率的快取資料搜尋策略。另外，我們也針對Snoop2無一致性快取記憶體系統的幾個實現上可能的問題提出探討和解決方法。最後，實驗結果呈現出Snoop2無一致性快取記憶體系統在減少晶片外的頻寬和快取失誤的比率能有不錯的表現。本子計畫的另一主題為可重組架構網路晶片系統架構，為了達到應用程式個別最佳化的目標提出了可重組架構網路晶片系統架構，並採用了分段式環狀結構的技術。我們提出的架構可以根據不同應用程式的需求去動態的做到拓樸學的客製化。而本架構最主要的目的是藉由拓樸學的重組去節省功率消耗和傳輸延遲。而架構的重組是讓應用程式在執行時，透過線路切換的電路設計去達到此目標。並且保留了原有網路晶片的連接性，以便下次重組。與傳統的架構相比較下，本子計畫所提出的架構可以有效的改善功率消耗和傳輸延遲。

Today’s multicore (or manycore) systems face memory-intensive and communication-intensive challenges to limit its scalability. Traffic on DRAM accessing or tradition shared caches (L2/L3) dominates real-time performance and power envelope. Distributing the traffic and shortening the communication distance could efficiently slow down the bandwidth wall problem.In this work, we promote the concept of hierarchical cache sharing for load-balancing and communication enhancement, and a ’Snoop2 Non-Uniform Cache Architecture’(Snoop2-NUCA) is proposed to flexibly share L1 caches. Snoop2-NUCA focus on providing an efficient optimization way that is to maximize the utilization of cache subsystem and a efficient data location search policy.In experiments, a 8-core multicore subsystem for multiple threads collaborative execution is modeled with several L1/L2 cache configurations. The results show Ideal architecture can reduce external memory bandwidth and L1 miss rate compared with traditional cache hierarchy designs.Another topic is a reconfigurable Network-on-Chip (NoC) architecture and segmented ring technique with application specific in the network topology. The proposed architecture can be customized its topology with traffic loading of different applications dynamically. This research seeks to reduce power consumption and latency in NoC architecture by topology reconfiguration. The architecture can tailor its topology by using energy-efficient switches based on circuit-switching at run-time. The NoC connectivity should also be preserve. Compare to traditional architectures, this architecture can effectively improve the NoC power consumption and latency.