應用於立體視訊之智慧型通訊系統研究-子計畫五：應用於立體視訊之智慧型通訊系統中系統記憶體設計與電路實現( I )

Abstract

隨著多媒體通訊系統的蓬勃發展，立體視訊之智慧型通訊系統將會是未來的趨勢。因此，晶片上不僅需要放置更多、更快且低功耗的記憶體來提供儲存資料，此記憶體也必須具備可以同時支援智慧型通訊系統中多個不同使用者的情境。我們將針對立體視訊之智慧型通訊系統，提出一個系統記憶體（包括多執行序檔案暫存器、分散式記憶體、集中式記憶體、快取記憶體、內容可定址記憶體及記憶體管理單元）設計與電路實現，配合針對多個不同使用者記憶體管理機制，以期達到記憶體頻寬的最佳化。在電路設計方面，將著重於低功耗之設計及抗製程電壓溫度變異設計，以解決奈米電路實現時所將遇到之瓶頸。另外，為了更有效率地管理功耗，我們將設計功率管理單元，並且使之與記憶體管理單元相整合。此外，我們也將研究低功率多執行序檔案暫存器及內容可定址記憶體，並將提出新的電路架構以減少檔案暫存器之面積與將低功率之消耗。我們將在第一年度研發記憶體元件及功率管理單元關鍵區塊。第二年度則完成多處理緒暫存器設計及內容可定址記憶體。第三年整合系統記憶體及功率控管單元，並參酌其他子計畫的規格訂定來完成最後系統記憶體最終的細部架構。本計畫在本年度已完成一個可操作在低電壓的512Kb的靜態隨機存取記憶陣列，此陣列是使用一個具有無讀取干擾跟資料感測寫入幫助的8T靜態隨機存取記憶單元、可調式讀取/寫入時間追蹤複製電路及漣波位元線讀取架構跟區域位元線，提高此記憶體陣列的讀取及寫入的穩定性跟能力。

In multimedia communication systems, 3D multimedia intelligent communication system is inevitably a major trend in the future. Therefore, large amounts of high speed and low power memories are indispensable for multi-core SoCs. Therefore, we will develop a system memory hierarchy (including multi-thread register file, distributed memory, centralized memory, content addressable memory (CAM), and memory management unit) for 3D multimedia intelligent communication system. With the circuit and architecture co-design, we will propose dynamic scheduling mechanisms for memory allocation and bandwidth. Moreover, for achieving better power control, we will provide a power management unit for the memory management unit. We will have further investigation on a low power multi-thread register file and CAM, and will provide novel circuit structures to reduce the power consumption of the register file and CAM.In the first year, we will develop key elements of the system memory units and power management unit. In the second year, we will complete the multi-thread register file and energy-efficient CAM macro. In the third year, we will integrate the system memory and power management unit. Accordingly, we will reference protocols of other sub-projects to complete the final detailed structure of the memory system. In the first year, a 512Kb low VDDMIN SRAM with a disturb-free and data-aware write-assist (DAWA) 8T bit-cell has been implemented. The cross-point structure of this 8T cell can eliminate the half-select disturb and support the bit-interleaving structure. The DAWA 8T SRAM, adaptive read/write time tracing replica circuit and ripple bit-line read scheme can enhance both the read-stability and write-ability for low operation voltage.