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dc.contributor.author陳紹基en_US
dc.contributor.authorCHEN SAU-GEEen_US
dc.date.accessioned2014-12-13T10:43:01Z-
dc.date.available2014-12-13T10:43:01Z-
dc.date.issued2011en_US
dc.identifier.govdocNSC100-2220-E009-026zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/99556-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=2310916&docId=361189en_US
dc.description.abstract本計畫至目前為止產出諸多成果,以下列出四個較主要之成果: (1) 提出一個超高產出率(throughput)之快速富利葉轉換(FFT)處理器,具低面積、低功耗等特性,其效能優於目前文獻上所載各式FFT處理器之性能。(2) 分別提出一個四倍平行和八倍平行具面積效率之快速濾波演算法架構,與文獻上所載濾波器相比,此架構適用於各種長度之濾波器,且複雜度低。(3) 提出之改良符元式的碼書波束成形的方法具有比現有技術更低複雜度但具有同樣效能。(4) 所提出的GA-MP與目前文獻上效能最佳的演算法做比較,此兩種演算法都能接近ML解,但我們的方法仍略勝一籌,而且我們所提出的方法其複雜度較低且易於實現。上述成果除了有些已經有被IEEE期刊論文及會議論文接受外,尚有一些在整理發表中,成果獲得專業肯定。zh_TW
dc.description.abstractBased on the codebook beamforming scheme in IEEE 802.15.3c, we propose a low-complexity codebook beamforming with angle-of-departure estimation (CB-AoDE) technique along with its analysis for enhancing the performance with a much lower computational complexity compared with the optimal beamforming. The experimental results show that CB-AoDE can outperform the existing codebook beamforming by up to 1.8dB in the BER performance. Besides, a scheme for blind joint estimations of residual carrier frequency (RCFO) and symbol timing offsets (STO) is proposed which doesn’t need the assistance of UW, while it can achieve the ideal estimation performance. This project also proposes a high data-rate and low-complexity reconfigurable multi-mode and multi-stream parallel filter architectures, which can be appropriately configured to meet the front-end filtering specifications of various communication systems. Next, this project presents a high-throughput FFT processor for SDR (Soft-defined Radio) application. The processor has low complexity and high operation speed due to its optimized pipelined structure. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. The EDA synthesis results show that the whole FFT processor area is only 1.2 mm2, and the power consumption is 15.5 mW with 90nm process. The SQNR performance is over 70 dB with 16-bit wordlength implementation for each FFT length.Finally, for channel coding, although MP (Message Passing) algorithm family have already good decoding performances, they do not perform as good as the maximum likelihood (ML) decoding. This project proposes a GA-MP algorithm based on the concept of genetic algorithm and MP algorithm. The decoding performance of GA-MP decoding is close to the ML decoding for various parity check matrices.en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject無線個人區域網路zh_TW
dc.subject波束成形zh_TW
dc.subject波束編碼簿zh_TW
dc.subject盲目估測zh_TW
dc.subject剩餘載波頻率偏移zh_TW
dc.subject符元取樣偏移zh_TW
dc.subject精密同步zh_TW
dc.subject軟體無線電zh_TW
dc.subject前端濾波運算zh_TW
dc.subject快速傅立葉轉換zh_TW
dc.subject低密度奇偶校驗碼zh_TW
dc.subject基因演算法zh_TW
dc.subject最大可能性解碼zh_TW
dc.subject訊息傳遞zh_TW
dc.subjectWPAN(Wireless Personal Area Network)en_US
dc.subjectBeamformingen_US
dc.subjectBeam Codebooken_US
dc.subjectResidual Carrier Frequency Offset (RCFO)en_US
dc.subjectSymbol Timing Offset (STO)en_US
dc.subjectFine Synchronizationen_US
dc.subjectSDRen_US
dc.subjectfront-end filteren_US
dc.subjectFIR filteren_US
dc.subjectFast filtering algorithmen_US
dc.subjectFFTen_US
dc.subjectLDPC codeen_US
dc.subjectGenetic algorithmen_US
dc.subjectMaen_US
dc.title次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP-子計畫二:前瞻無線寬頻、具十億位元以上接收功能之綠能基頻前端訊號編解碼器研究設計( I )zh_TW
dc.titleDesign of Green Baseband Front-End Signal Coder/Decoder for Advanced Broadband Multi-Gbps Wireless Communicationen_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系及電子研究所zh_TW
Appears in Collections:Research Plans