標題: | 高效能薄膜電晶體和以薄膜電晶體為基底之非揮發性記憶體元件 High-Performance Tft and Tft-Based Non-Volatile Memory Devices |
作者: | 荊鳳德 CHIN ALBERT 國立交通大學電子工程學系及電子研究所 |
關鍵字: | 高介電係數氧化鋁鑭(LaAlO3)介電質;低溫多晶矽薄膜電晶體(TFT);高驅動電流;低臨界電壓(Vt);次臨界擺福(SS) |
公開日期: | 2011 |
摘要: | 高驅動電流對於高操作電流的有機發光二極體是必要的。雖然可以藉由近期發展的
氧化鎵銦鋅(IGZO)薄膜電晶體來實現,但是氧化鎵銦鋅(IGZO)最基本的限制在於高成
本,並且在地表上所能提供的元素量有限。除此之外,薄膜電晶體在顯示系統面板(SoP)
的設計上對於非揮發性記憶體的功能是必要的,但是由於氧化鎵銦鋅(IGZO)的較大能隙
使得電洞濃度較低而導致較難抹除。這次JST-NSC 提案的目標是共同地發展高驅動電流
且低成本的矽基底薄膜電晶體和以薄膜電晶體為基底的非揮發性記憶體元件。高介電係
數閘極介電質和高移動率通道都是用來達到高驅動電流薄膜電晶體的方法。我們早在
2005 年時就是使用高介電係數多晶矽薄膜電晶體的先驅者。高移動率可藉由形成金屬摻
雜的矽叢聚或者是日本AIST 所發展出的金屬壓縮矽叢聚。藉由在國立交通大學的元件
製程和AIST 所發展出的新通道物質在新研究領域上是非常完美的合作模式。在證明出
矽叢聚薄膜電晶體有良好的特性之後,我們也將用我們發展出的高介電係數雙層能障和
雙層補陷層的電荷補陷設計的快閃記憶體(CTEF)來製造氮補陷非揮發性記憶體。對於高
密度的三維快閃記憶體來說,以薄膜電晶體為基底的非揮發性記憶體是非常重要的。若
此共同合作的計畫藉由JST-NSC 來提供資金將會藉由高移動率的矽奈米叢聚在科學上有
重大的貢獻和薄膜電晶體的改善。這將會是第一個高效能薄膜電晶體奈米元件的演進。
藉由不使用高成本且供量不足的IGZO,這對於高效能薄膜電晶體顯示器產業來說將會是
重大的經濟貢獻。 High drive current TFT is especially required for the high operation current OLED. Although this can be realized by the newly developed InGaZnO (IGZO) TFT, the fundamental limitation of IGZO device is the relative high cost and lacking of sufficient material supply of In in Earth’s crust. Besides the TFT, the required non-volatile memory (NVM) function is also necessary for System on Panel (SoP) designs, but the IGZO NVM device is difficult to erase due to the small hole concentration by large energy bandgap. The objectives of this JST-NSC proposal are to jointly develop high drive current low-cost Si-based TFT and TFT-based NVM devices. The methodology to reach the high drive current TFT is to use both high-k gate dielectric and high mobility channel. We previously pioneered the high-k poly-Si TFT device starting at 2005. The high mobility can be achieved by forming the Metal-doped Si Clusters or Metal-Encapsulating Si Cage Clusters developed at AIST Japan. Such device processing at National Chiao Tung University and new channel material development at AIST is the perfect collaboration mode for frontier research. After demonstrating the good performance of Si-clusters TFT, we shall also fabricate the nitride-trapping NVM using high-κ double-barrier and double-trapping layers Charge-Trapping-Engineered Flash (CTEF) invented by us. Such TFT-based NVM device is also important for very high density three-dimensional (3D) flash memory. If the joint proposal is funded by JST-NSC, this will have important scientific contribution to bring the high mobility Si Nano clusters into TFT device improvement. This should be the first Nano device for high performance TFT evolution. This should have important economic contribution for high performance TFT-display industry without using high cost and insufficient material supply IGZO. |
官方說明文件#: | NSC99-2923-E009-001-MY3 |
URI: | http://hdl.handle.net/11536/99586 https://www.grb.gov.tw/search/planDetail?id=2217840&docId=355222 |
顯示於類別: | 研究計畫 |