Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 鄭晃忠 | en_US |
dc.contributor.author | CHENG HUANG-CHUNG | en_US |
dc.date.accessioned | 2014-12-13T10:43:21Z | - |
dc.date.available | 2014-12-13T10:43:21Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.govdoc | NSC99-2221-E009-168-MY3 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/99702 | - |
dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=2201219&docId=350705 | en_US |
dc.description.abstract | 未來終端產品發展必然走向輕薄短小、多功能、高效能、低耗電、光機電整合及異質整合的 需求與趨勢,才能滿足市場需求。相較SoC(System on Chip)所需之成本與時間相對較高,過程掌 控較為困難,而SiP(System in Package)技術風險小,適合用於大量與可長時間整合之應用。SiP 已衍生出新一代的Cavity PoP (Package on package)和Embedd-ed Die,並朝向Fan in PoP 及矽晶直 通孔(Through Silicon Via, TSV)發展,遂整合3D Package 及TSV 技術的三維積體電路(3D IC)將 可符合消費性電子產品市場多樣化需求。 在本計畫中我們將以極佳的導電性、超高熱傳導係數與高承受應力的奈米碳管用做為填充 TSV 的材料,以改善電傳導特性、增加導熱效率與加強整體結構的機械強度,甚至在未來更深的 高寬比下,比起現有的銅電鍍能更有效率的填充奈米碳管於TSV 內。本計畫執行將分為外部植入 (CNT Protrusion in TSV)與直接成長於孔洞(CNT Direct Growth in TSV)的方式進行,透過製程參數 最佳化以成長高品質之奈米碳管,與其他子計畫合作整合元件與填充奈米碳管的矽晶直通孔結 構,並測試其相關特性及可靠度分析。本計畫研發之矽晶直通孔結構將以高導電、高導熱、強應 力性做為目標,以提升國內對於三維積體電路及矽晶直通孔之發展。 | zh_TW |
dc.description.abstract | Apparently, the development of terminal products will be focused on miniature, multi-function, high-efficiency, low power consumption, Opto-mechatronic integration and even heterogeneous integration. Comparing to the high-cost and long-duration SoC (System on Chip) technology, SiP (System in Package) with lower technological risks is adequate for the mainstream fabrication. Nowadays, SiP has developed to Cavity PoP (Package on package) and Embedded Die technologies, and it will move on to Fan in PoP and Through Silicon Via (TSV) in the next generation. Therefore, present semiconductor industry is entering a new era of 3D integration and TSV technology in order to satisfy the consumer-electronics market demand. In this project, carbon nanotubes (CNTs), with high electrical conductivity, excellent heat conduction, and strong stress endurance, are utilized to through silicon via (TSV). Furthermore, we can pack carbon nanotubes in higher aspect ratio via more effectively than cooper electroplating. The experiment is divided into two parts: 1) CNT protrusion in TSV and 2) CNT direct growth in TSV. By optimizing the growth parameter, superior quality carbon nanotubes could be achieved. Finally, the TSV structure with carbon nanotubes will be integrated with solid-state devices, and the performance and reliability will be tested. The ultimate goal is to attain a high value of electrical conductivity, thermal conductivity, and mechanical strength. With completing this project, we hope the technology of TSV and 3D IC in Taiwan can be promoted. | en_US |
dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.subject | 奈米碳管 | zh_TW |
dc.subject | 矽晶直通孔 | zh_TW |
dc.subject | 三維積體電路 | zh_TW |
dc.subject | Carbon nanotube | en_US |
dc.subject | Through-silicon-via (TSV) | en_US |
dc.subject | 3D IC | en_US |
dc.title | 奈米碳管應用於三維積體電路(3D IC)之矽晶直通孔(TSV)結構之技術探討與研究 | zh_TW |
dc.title | Studies and Investigation of Technology Development for through Silicon VI a (Tsv) Structure of Three-Dimension Integrated Circuits (3d Ic) with Carbon Nanotube | en_US |
dc.type | Plan | en_US |
dc.contributor.department | 國立交通大學電子工程學系及電子研究所 | zh_TW |
Appears in Collections: | Research Plans |