平行運算電子設計自動化技術研究-子計畫六：平行化多核心系統測試方法( I )

Abstract

一直以來，平行化一向是增加系統生產量的最重要原則之一。隨著半導體晶片的效能不斷增加，價格不斷減低，將多個處理器 (或核心) 整合進單一系統中，以增進計算平行化與系統生產量，變成一個更容易可實現、更有效率、並更符合成本之技巧。多核心系統的效能，會嚴重的取決於以下兩點:(1) 記憶體的頻寬，以及 (2) 多核心之間通訊頻寬。為了要分別改善記憶體頻寬與通訊頻寬，過去有許多的研究在討論多埠靜態記憶體 (multi-port SRAM，以及晶片網路 (network-on-chip)。隨著多埠靜態記憶體與晶片網路的技術演進，其所衍生之錯誤模型與測試方法都必須得隨之調整，然而現今文獻中對此並無具體研究成果。因此，本子計畫之主題，將會圍繞在多核心系統中，多埠靜態記憶體測試以及晶片網路測試之上。

Parallelism has been the one of the most important principles to increase a system’s throughput in the past. With the continually decreasing price and increasing performance of silicon chips for advanced technologies, incorporating multiple processors into a system has become a more feasible, effective, and economic solution to further explore the computation parallelism of a system as well as its throughput. The performance of amultiple-core system can be significantly affected by the following two major factors: (1) the bandwidth of its memory and (2) the bandwidth of its communication between different cores. To improve the memory bandwidth and the communication bandwidth, significant research efforts have been put into the area of multi-port SRAM designs and network-on-chip (NOC) designs in the past, respectively. As the technologies in multi-port SRAM and NOC keep on advancing, their corresponding fault models as well as testingmethodologies also need to be adjusted accordingly. Therefore, the focus of this sub-project will be on testing the multi-port SRAMs and NOCs for a multi-core system.