標題: 前瞻性銻化物異質材料場效電晶體及其高速低功率元件與可調式高頻電路應用之研究---總計畫
Integration of Advanced Antimony-Based Heter-Material Field Effect Transistors for High-Speed Low-Power and Tunability High-Frequency Circuit Applications
作者: 張翼
CHANG EDWARD YI
國立交通大學材料科學與工程學系(所)
關鍵字: 銻化物;量子井電晶體;微波相位陣列收發模組;電磁干擾;多晶片模組
公開日期: 2010
摘要: 本研究計畫的目標是整合交大與中央兩校資源,發展低功耗且高效率之微波相位陣 列收發模組之中的關鍵性元組件及電路,並進行相關製程元件與系統整合之研究。低功 耗與高效率之組件設計在大型相位陣列的衛星通訊及氣象雷達等應用極為重要。 子計畫一主要負責的是銻化物材料MBE 磊晶成長(包括N 型及P 型)。子計畫五 將以子計畫一所成長的磊晶為基礎製作次微米及奈米等級(40 nm)的QWFET。子計畫 二將開發BiFET 高性能微波電路及高速低功耗混合電路,並與子計畫三則將使用子計畫 一與五所發展的Sb-based QWFET 製程,並配合中央大學電機系現有的InP-based HBT 製程,應用於相位陣列收發模組主動電路的設計,同時協助銻化物QWFET 及磷化銦 HBT 的電路模型建立,以提供子計畫一與五製程優化的參考。另外,子計畫三將使用脈 衝雷射沉積鐵性材料(ferroic materials, 包括鐵電與鐵氧磁體)薄膜,並應用於相位陣 列收發模組的被動電路設計。子計畫五將使用覆晶技術來結合主動及被動微波電路以組 成一低功耗相位陣列模組。子計畫四將針對此一系統級封裝之微波電路模組的電源完整 性及電磁干擾作分析,並使用子計畫三發展的鐵性材料進行電源供應網路與EMI filter 設計,搭配子計畫五的覆晶技術將電源完整性解決方案有效整合於晶片封裝結構中,確 保低功耗QWFET 電路能於低供應電壓下穩定操作。 經由本計畫之成功之整合,奠定我國在Sb-based FETs 相關產業上之領導地位,將 Sb-based FETs 關鍵技術在國內生根。
The object of this work is to integrate the resources between NCTU and NCU and to develop of key components and circuit for phase array receiver module for low-power applications. It is very important to design a low-power and high-efficiency large phase array module for satellite communication and atmosphere radar. The sub-project (1) is to grow Sb-based device epitaxy structures includes n/p-channel. For sub-project (5), it is to fabricate deep-nano gate lengths QWFETs ranging from 30, 40, 50, 60, and 80 nm. The sub-project (5) can provide electric characterizations to optimize epitaxial structures in sub-project (1). High-performance BiFETs RF circuit and low-power-consumption mix circuit will be developed in the sub-project (2). This work design active circuit for phase array module applications combining Sb-based QWFETs and NCU EE InP-HBTs. In addition, it assists the development of modeling circuit of Sb-based QWFETs and HBTs. Ferroic materials are deposited using pulse-laser deposition system to fabricate passive circuit for phase array module applications. The active and passive circuit will be integrated using flip-chip techniques to form a low-power-consumption phase array. Power integrity and electromagnetic interference of system-on-packaging module are analyzed in the sub-project (4). Finally, power distribution network and EMI filter will be designed using ferroic materials in sub-project (3) in order to make sure the QWFETs operating in low supply voltage.
官方說明文件#: NSC99-2221-E009-170-MY3
URI: http://hdl.handle.net/11536/99886
https://www.grb.gov.tw/search/planDetail?id=2116961&docId=338584
Appears in Collections:Research Plans