A 17-nW, 0.5V, 500S/s, Rail-to-Rail SAR ADC with 8.1 Effective Number of Bits

dc.citation.woscount	0	en_US
dc.contributor.author	Kuo, Rong-Zhou	en_US
dc.contributor.author	Hong, Hao-Chiao	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.date.accessioned	2015-12-02T03:00:49Z
dc.date.available	2015-12-02T03:00:49Z
dc.date.issued	2014-01-01	en_US
dc.description.abstract	This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 mu m CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.	en_US
dc.identifier.isbn	978-1-4799-2776-0	en_US
dc.identifier.issn		en_US
dc.identifier.journal	2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/128472
dc.identifier.wosnumber	WOS:000356616400047	en_US
dc.language.iso	en_US	en_US
dc.title	A 17-nW, 0.5V, 500S/s, Rail-to-Rail SAR ADC with 8.1 Effective Number of Bits	en_US
dc.type	Proceedings Paper	en_US

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