Systematic layout planning: a study on semiconductor wafer fabrication facilities
| dc.citation.epage | 1372 | en_US |
| dc.citation.issue | 11-12 | en_US |
| dc.citation.spage | 1360 | en_US |
| dc.citation.volume | 20 | en_US |
| dc.citation.woscount | 23 | |
| dc.contributor.author | Yang, TH | en_US |
| dc.contributor.author | Su, CT | en_US |
| dc.contributor.author | Hsu, YR | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.date.accessioned | 2014-12-08T15:20:26Z | |
| dc.date.available | 2014-12-08T15:20:26Z | |
| dc.date.issued | 2000 | en_US |
| dc.description.abstract | This paper proposes to use Muther's systematic layout Planning Procedure as the infrastructure to solve a fab layout design problem. A multiple objective decision making;ng tool, analytic hierarchy process, is then proposed to evaluate the design alternatives. The proposed procedure is illustrated to be a viable approach for solving a fab layout design problem through a real-world case study. It features both the simplicity of the design Process and the objectivity of the multiple-criteria evaluation process as opposed to existing solution methodologies. | en_US |
| dc.identifier.issn | 0144-3577 | en_US |
| dc.identifier.journal | INTERNATIONAL JOURNAL OF OPERATIONS & PRODUCTION MANAGEMENT | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/14531 | |
| dc.identifier.wosnumber | WOS:000165998000007 | |
| dc.language.iso | en_US | en_US |
| dc.subject | layout | en_US |
| dc.subject | semiconductors | en_US |
| dc.subject | material handling | en_US |
| dc.subject | analytical hierarchy process | en_US |
| dc.subject | decision making | en_US |
| dc.title | Systematic layout planning: a study on semiconductor wafer fabrication facilities | en_US |
| dc.type | Article | en_US |
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