9.5 GHz GaInP/GaAs HBT divide-by-two frequency divider using super-dynamic D-type flip-flop technique
| dc.citation.epage | 707 | en_US |
| dc.citation.issue | 13 | en_US |
| dc.citation.spage | 706 | en_US |
| dc.citation.volume | 43 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Wei, H.-J. | en_US |
| dc.contributor.author | Meng, C. | en_US |
| dc.contributor.author | Chang, Y. W. | en_US |
| dc.contributor.author | Huang, G.-W | en_US |
| dc.contributor.department | 電信工程研究所 | zh_TW |
| dc.contributor.department | Institute of Communications Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:13:49Z | |
| dc.date.available | 2014-12-08T15:13:49Z | |
| dc.date.issued | 2007-06-21 | en_US |
| dc.description.abstract | A frequency divider with super-dynamic D-type flip-flop is demonstrated in 2 mu m GaInP/GaAs HBT (f(T) = 40 GHz) technology. By biasing the HBT devices around the peak transit-time frequency (f(T)), the operating frequency of a D-FT with ECNFP (emitter-coupled negative feedback pairs) can be improved. At a supply voltage of 5 V a divide-by-two function of 9.5 GHz is achieved. | en_US |
| dc.identifier.doi | 10.1049/el:20070727 | en_US |
| dc.identifier.issn | 0013-5194 | en_US |
| dc.identifier.journal | ELECTRONICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1049/el:20070727 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/10674 | |
| dc.identifier.wosnumber | WOS:000248750000007 | |
| dc.language.iso | en_US | en_US |
| dc.title | 9.5 GHz GaInP/GaAs HBT divide-by-two frequency divider using super-dynamic D-type flip-flop technique | en_US |
| dc.type | Article | en_US |