ON THE DESIGN OF VLSI ARCHITECTURES FOR PARALLEL EXECUTION OF DO LOOPS
| dc.citation.epage | 399 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 393 | en_US |
| dc.citation.volume | 8 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | CHEN, Z | en_US |
| dc.contributor.author | CHANG, CC | en_US |
| dc.contributor.author | CHIA, TL | en_US |
| dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
| dc.contributor.department | Institute of Computer Science and Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:05:35Z | |
| dc.date.available | 2014-12-08T15:05:35Z | |
| dc.date.issued | 1990-04-01 | en_US |
| dc.identifier.issn | 0743-7315 | en_US |
| dc.identifier.journal | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/4132 | |
| dc.identifier.wosnumber | WOS:A1990CY87900011 | |
| dc.language.iso | en_US | en_US |
| dc.title | ON THE DESIGN OF VLSI ARCHITECTURES FOR PARALLEL EXECUTION OF DO LOOPS | en_US |
| dc.type | Note | en_US |
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