Spatially resolving the hot carrier degradations of poly-Si thin-film transistors using a novel test structure

Abstract

A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HQ degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified.