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Parallelism exploitation in superscalar multiprocessing

dc.citation.epage264en_US
dc.citation.issue4en_US
dc.citation.spage255en_US
dc.citation.volume145en_US
dc.citation.woscount1
dc.contributor.authorLu, NPen_US
dc.contributor.authorChung, CPen_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.date.accessioned2014-12-08T15:48:55Z
dc.date.available2014-12-08T15:48:55Z
dc.date.issued1998-07-01en_US
dc.description.abstractTo exploit more parallelism in programs, superscalar multiprocessor systems, which exploit both fine-grained and coarse-grained parallelism have been the trend in designing high-speed computing systems. Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems. This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism. This simulator was used to run four applications chosen from the SPLASH-2 benchmark suite, and collected some performance data to investigate the parallelism exploitation capability of the superscalar multiprocessor systems in various configurations. It was observed that the instruction-level and task-level parallelism in programs can be exploited well by a moderate degree of superscalar processing and a high degree of multiprocessing. For example, the speedup of a 32-way multiprocessor with eight-issue processors can be over 200 relative to a single-issue uniprocessor.en_US
dc.identifier.issn1350-2387en_US
dc.identifier.journalIEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUESen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/32537
dc.identifier.wosnumberWOS:000075323100002
dc.language.isoen_USen_US
dc.subjectparallel processingen_US
dc.subjectmultiprocessing systems systemsen_US
dc.subjectsuperscalar multiprocessingen_US
dc.titleParallelism exploitation in superscalar multiprocessingen_US
dc.typeArticleen_US

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