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Characteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistors

dc.citation.epage141en_US
dc.citation.issue2en_US
dc.citation.spage139en_US
dc.citation.volume30en_US
dc.citation.woscount15
dc.contributor.authorSheu, Jeng-Tzongen_US
dc.contributor.authorHuang, Po-Chunen_US
dc.contributor.authorSheu, Tzu-Shiunen_US
dc.contributor.authorChen, Chen-Chiaen_US
dc.contributor.authorChen, Lu-Anen_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department材料科學與工程學系奈米科技碩博班zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentGraduate Program of Nanotechnology , Department of Materials Science and Engineeringen_US
dc.date.accessioned2014-12-08T15:10:04Z
dc.date.available2014-12-08T15:10:04Z
dc.date.issued2009-02-01en_US
dc.description.abstractWe have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH(3) plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 10(8)), and a virtual absence of drain-induced barrier lowering (1.3 mV/V).en_US
dc.identifier.doi10.1109/LED.2008.2009956en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2008.2009956en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/7681
dc.identifier.wosnumberWOS:000262861600014
dc.language.isoen_USen_US
dc.subjectGate-all-around (GAA)en_US
dc.subjectnanowire (NW)en_US
dc.subjectplasma treatmenten_US
dc.subjectshort-channel effects (SCEs)en_US
dc.subjectthin-film transistor (TFT)en_US
dc.titleCharacteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistorsen_US
dc.typeArticleen_US

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