OPTIMAL TILE PARTITION FOR SPACE REGION OF INTEGRATED-CIRCUITS GEOMETRY
| dc.citation.epage | 153 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 145 | en_US |
| dc.citation.volume | 140 | en_US |
| dc.citation.woscount | 2 | |
| dc.contributor.author | HSIAO, PY | en_US |
| dc.contributor.author | LIN, CY | en_US |
| dc.contributor.author | SHEW, PW | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:04:32Z | |
| dc.date.available | 2014-12-08T15:04:32Z | |
| dc.date.issued | 1993-05-01 | en_US |
| dc.description.abstract | An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas our OTP allows overlapping. This paper also shows three theorems with rigorous proofs and experimental results to obtain the minimal number of the space tiles through the OTP. Moreover, a dynamic plane-sweep algorithm based on region query for the OTP has been developed. Using the OTP, the memory efficiency and the local query operations of the original corner stitching data structure have been enhanced. | en_US |
| dc.identifier.issn | 0143-7062 | en_US |
| dc.identifier.journal | IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3032 | |
| dc.identifier.wosnumber | WOS:A1993LW32100001 | |
| dc.language.iso | en_US | en_US |
| dc.subject | VLSI LAYOUT | en_US |
| dc.subject | CHANNEL PARTITION | en_US |
| dc.subject | CORNER STITCHING | en_US |
| dc.subject | TILE GENERATION | en_US |
| dc.title | OPTIMAL TILE PARTITION FOR SPACE REGION OF INTEGRATED-CIRCUITS GEOMETRY | en_US |
| dc.type | Article | en_US |