Verification of pin-accurate port connections
| dc.citation.epage | 486 | en_US |
| dc.citation.issue | 5 | en_US |
| dc.citation.spage | 478 | en_US |
| dc.citation.volume | 25 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Lee, Geeng-Wei | en_US |
| dc.contributor.author | Huang, Juinn-Dar | en_US |
| dc.contributor.author | Wang, Chun-Yao | en_US |
| dc.contributor.author | Jou, Jing-Yang | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:11:01Z | |
| dc.date.available | 2014-12-08T15:11:01Z | |
| dc.date.issued | 2008-09-01 | en_US |
| dc.description.abstract | Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow. | en_US |
| dc.identifier.doi | 10.1109/MDT.2008.149 | en_US |
| dc.identifier.issn | 0740-7475 | en_US |
| dc.identifier.journal | IEEE DESIGN & TEST OF COMPUTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/MDT.2008.149 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/8437 | |
| dc.identifier.wosnumber | WOS:000259673900009 | |
| dc.language.iso | en_US | en_US |
| dc.title | Verification of pin-accurate port connections | en_US |
| dc.type | Article | en_US |