A design strategy for short gate length SOI MESFETs

Abstract

A design strategy for short gate length, self-aligned Si-SOI MESFETs is proposed, in which the design considerations for the important device parameters of the SOI MESFET are studied by using a 2D numerical simulator. It is shown that the sub-threshold I-ds-V-gs characteristics can be used to determine the thickness of silicon film for a given channel doping level under a specified threshold voltage. Moreover, the 2D effect can be suppressed by reducing the thickness of buried oxide to improve the bottom-gate controllability over the channel charges. Moreover, it is shown the backgate bias is also an important controllable parameter for modulating the characteristics of the SOI MESFET in both sub-threshold and saturation regions. An example for designing a very short gate length (0.1 mu m) SOI MESFET has been carried out to verify this strategy. It is shown that the proposed strategy does provide an effective procedure for designing an Si-SOI MESFET with high performance.