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Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure

dc.citation.epage1097en_US
dc.citation.issue8en_US
dc.citation.spage1095en_US
dc.citation.volume32en_US
dc.citation.woscount6
dc.contributor.authorWu, Chun-Yuen_US
dc.contributor.authorLiu, Yen-Tingen_US
dc.contributor.authorLiao, Ta-Chuanen_US
dc.contributor.authorYu, Ming H.en_US
dc.contributor.authorCheng, Huang-Chungen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:28:53Z
dc.date.available2014-12-08T15:28:53Z
dc.date.issued2011-08-01en_US
dc.description.abstractHigh-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.en_US
dc.identifier.doi10.1109/LED.2011.2158053en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2011.2158053en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/20860
dc.identifier.wosnumberWOS:000293710400034
dc.language.isoen_USen_US
dc.subjectField-enhanced nanowire (FEN)en_US
dc.subjecthigh-ken_US
dc.subjectpoly-Sien_US
dc.subjectsystem-on-panel (SOP)en_US
dc.subjectthin-film transistors (TFTs)en_US
dc.subjecttrapping-charge memoryen_US
dc.titleNovel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structureen_US
dc.typeArticleen_US

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