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Fast SIFT Design for Real-Time Visual Feature Extraction

dc.citation.epage3167en_US
dc.citation.issue8en_US
dc.citation.spage3158en_US
dc.citation.volume22en_US
dc.citation.woscount4
dc.contributor.authorChiu, Liang-Chien_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.contributor.authorChen, Jiun-Yenen_US
dc.contributor.authorChang, Nelson Yen-Chungen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:31:04Z
dc.date.available2014-12-08T15:31:04Z
dc.date.issued2013-08-01en_US
dc.description.abstractVisual feature extraction with scale invariant feature transform (SIFT) is widely used for object recognition. However, its real-time implementation suffers from long latency, heavy computation, and high memory storage because of its frame level computation with iterated Gaussian blur operations. Thus, this paper proposes a layer parallel SIFT (LPSIFT) with integral image, and its parallel hardware design with an on-the-fly feature extraction flow for real-time application needs. Compared with the original SIFT algorithm, the proposed approach reduces the computational amount by 90% and memory usage by 95%. The final implementation uses 580-K gate count with 90-nm CMOS technology, and offers 6000 feature points/frame for VGA images at 30 frames/s and similar to 2000 feature points/frame for 1920x1080 images at 30 frames/s at the clock rate of 100 MHz.en_US
dc.identifier.doi10.1109/TIP.2013.2259841en_US
dc.identifier.issn1057-7149en_US
dc.identifier.journalIEEE TRANSACTIONS ON IMAGE PROCESSINGen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TIP.2013.2259841en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/22155
dc.identifier.wosnumberWOS:000321926600020
dc.language.isoen_USen_US
dc.subjectFeature extractionen_US
dc.subjectSIFTen_US
dc.subjectVLSI designen_US
dc.titleFast SIFT Design for Real-Time Visual Feature Extractionen_US
dc.typeArticleen_US

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