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RECESSED-GATE ALGAAS/INGAAS/GAAS PSEUDORMORPHIC HEMT WITH SI-PLANAR-DOPED ETCH-STOP LAYER

dc.citation.epage594en_US
dc.citation.issue7en_US
dc.citation.spage592en_US
dc.citation.volume31en_US
dc.citation.woscount1
dc.contributor.authorLAN, WHen_US
dc.contributor.authorLIN, WJen_US
dc.contributor.authorPENG, CKen_US
dc.contributor.authorCHEN, SSen_US
dc.contributor.authorTU, SLen_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:03:29Z
dc.date.available2014-12-08T15:03:29Z
dc.date.issued1995-03-30en_US
dc.description.abstractAn improved slot etch technique based on an Si planar doped laver has been applied to gate recessing in the fabrication of AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (HEMTs). The devices exhibited comparable g(m) with much better breakdown and leakage behaviour than conventional pseudomorphic HEMT devices.en_US
dc.identifier.doi10.1049/el:19950374en_US
dc.identifier.issn0013-5194en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1049/el:19950374en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/2006
dc.identifier.wosnumberWOS:A1995QT82300058
dc.language.isoen_USen_US
dc.subjectHIGH ELECTRON MOBILITY TRANSISTORSen_US
dc.subjectETCHINGen_US
dc.titleRECESSED-GATE ALGAAS/INGAAS/GAAS PSEUDORMORPHIC HEMT WITH SI-PLANAR-DOPED ETCH-STOP LAYERen_US
dc.typeArticleen_US

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