TIMING-DRIVEN PARTIAL SCAN
| dc.citation.epage | 59 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 52 | en_US |
| dc.citation.volume | 12 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | JOU, JY | en_US |
| dc.contributor.author | CHENG, KT | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:03:04Z | |
| dc.date.available | 2014-12-08T15:03:04Z | |
| dc.date.issued | 1995-12-01 | en_US |
| dc.description.abstract | This partial scan approach reduces area overhead and performance degradation caused by test logic. Given an initial design that meets a target speed, the authors' algorithm selects a set of scan flip-flops that allows the circuit to meet performance requirements after the scan logic is added. if no such set exists, the algorithm selects a set that minimizes the total area increase caused by the scan logic and the subsequent performance optimization the circuit requires to meet target speed. | en_US |
| dc.identifier.doi | 10.1109/54.491238 | en_US |
| dc.identifier.issn | 0740-7475 | en_US |
| dc.identifier.journal | IEEE DESIGN & TEST OF COMPUTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/54.491238 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/1644 | |
| dc.identifier.wosnumber | WOS:A1995TF01400008 | |
| dc.language.iso | en_US | en_US |
| dc.title | TIMING-DRIVEN PARTIAL SCAN | en_US |
| dc.type | Article | en_US |