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A floating well method for exact capacitance-voltage measurement of nano technology

dc.citation.epage1544en_US
dc.citation.issue6en_US
dc.citation.spage1543en_US
dc.citation.volume50en_US
dc.citation.woscount0
dc.contributor.authorSu, HDen_US
dc.contributor.authorChiou, BSen_US
dc.contributor.authorWu, SYen_US
dc.contributor.authorChang, MHen_US
dc.contributor.authorLee, KHen_US
dc.contributor.authorChen, YSen_US
dc.contributor.authorChao, CPen_US
dc.contributor.authorSee, YCen_US
dc.contributor.authorSun, JYCen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:40:51Z
dc.date.available2014-12-08T15:40:51Z
dc.date.issued2003-06-01en_US
dc.description.abstractSmall gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.en_US
dc.identifier.doi10.1109/TED.2003.813329en_US
dc.identifier.issn0018-9383en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2003.813329en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/27845
dc.identifier.wosnumberWOS:000184249700017
dc.language.isoen_USen_US
dc.subjectcapacitance-voltageen_US
dc.subjectelectrical oxide thicknessen_US
dc.subjectfloating wellen_US
dc.subjectnano technologyen_US
dc.subjectultrathin oxideen_US
dc.titleA floating well method for exact capacitance-voltage measurement of nano technologyen_US
dc.typeArticleen_US

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