High-speed booth encoded parallel multiplier design
| dc.citation.epage | 701 | en_US |
| dc.citation.issue | 7 | en_US |
| dc.citation.spage | 692 | en_US |
| dc.citation.volume | 49 | en_US |
| dc.citation.woscount | 61 | |
| dc.contributor.author | Yeh, WC | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:45:04Z | |
| dc.date.available | 2014-12-08T15:45:04Z | |
| dc.date.issued | 2000-07-01 | en_US |
| dc.description.abstract | This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation. | en_US |
| dc.identifier.issn | 0018-9340 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTERS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/30400 | |
| dc.identifier.wosnumber | WOS:000088843800008 | |
| dc.language.iso | en_US | en_US |
| dc.subject | final adder | en_US |
| dc.subject | Booth encoding | en_US |
| dc.subject | multiple-level conditional-sum adder | en_US |
| dc.subject | and parallel multiplier | en_US |
| dc.title | High-speed booth encoded parallel multiplier design | en_US |
| dc.type | Article | en_US |