Demonstration and Electrical Performance Investigation of Wafer-Level Cu Oxide Hybrid Bonding Schemes
| dc.citation.epage | 1121 | en_US |
| dc.citation.issue | 8 | en_US |
| dc.citation.spage | 1119 | en_US |
| dc.citation.volume | 32 | en_US |
| dc.citation.woscount | 12 | |
| dc.contributor.author | Chen, Kuan-Neng | en_US |
| dc.contributor.author | Xu, Zheng | en_US |
| dc.contributor.author | Lu, Jian-Qiang | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:28:54Z | |
| dc.date.available | 2014-12-08T15:28:54Z | |
| dc.date.issued | 2011-08-01 | en_US |
| dc.description.abstract | Wafer-level Cu oxide hybrid bonding owns a number of merits, including simultaneous formations of electrical and mechanical bonds, underfill free, high alignment accuracy, increasing bond strength, and excellent reliability performance in 3-D integration. This letter demonstrates the fabrication of wafer-level Cu oxide hybrid bonding. Investigations of experimental and electrical simulation data of Cu oxide hybrid bonding structures are reported. Their alignment accuracy, frequency responses, and passive elements are compared for 3-D integration applications. | en_US |
| dc.identifier.doi | 10.1109/LED.2011.2157657 | en_US |
| dc.identifier.issn | 0741-3106 | en_US |
| dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/LED.2011.2157657 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/20882 | |
| dc.identifier.wosnumber | WOS:000293710400042 | |
| dc.language.iso | en_US | en_US |
| dc.subject | Hybrid wafer bonding | en_US |
| dc.subject | wafer level | en_US |
| dc.subject | 3-D integration | en_US |
| dc.title | Demonstration and Electrical Performance Investigation of Wafer-Level Cu Oxide Hybrid Bonding Schemes | en_US |
| dc.type | Article | en_US |