Jitter Measurement and Compensation for Analog-to-Digital Converters

Abstract

Clock jitter is measured and digitized by a stochastic time-to-digital converter (TDC). This jitter information is used to compensate the sampling error of an analog-to-digital converter (ADC) caused by the clock jitter. The following two system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. TDC calibrations for both scenarios are proposed. The calibrations are based on signal reconstruction and can be performed in the background. Both theoretical analyses and system simulations are provided to verify the proposed jitter compensation and TDC calibration techniques.